View R61503U_7810984.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev.1.1, march 29, 2007, page 1 of 186 specification R61503U 262,144-color, 176rgb x 220-dot graphics a-si tft liquid crystal panel controller driver rejxxxxxxx-xxxxz rev.1.1 march 29, 2007 ? index description ......................................................................................................... 6 features ......................................................................................................... 7 block diagram .................................................................................................... 9 pin function ........................................................................................................ 10 pad arrangement .............................................................................................. 16 chip size ......................................................................................................... 17 pad coordinates .................................................................................................. 18 bump size ......................................................................................................... 28 block function.................................................................................................... 29 1. system interface............................................................................................................... ................29 2. external display interface (rgb, vsync interfaces) ....................................................................30 3. address counter (ac)........................................................................................................... ...........30 4. graphics ram (gram)............................................................................................................ ......30 5. grayscale voltage generating circuit........................................................................................... ...30 6. timing generator............................................................................................................... ..............30 7. oscillator (osc) ............................................................................................................... ...............31 8. liquid crystal driver circuit.................................................................................................. ...........31 9. internal logic power supply regulator.......................................................................................... .....31 10. liquid crystal drive power supply circuit...................................................................................... ...31 11. nv memory ...................................................................................................................... ...............31 gram address map......................................................................................... 32 relation between gram addresses and positions on the screen (ss= ?0?, bgr= ?0?) .......................32 relation between gram data and display data (ss= ?0?, bgr= ?0?)................................................33 relation between gram address and position on the screen (ss= ?1?, bgr= ?1?) ............................36 relation between gram data and display data (ss= ?1?, bgr= ?1?)................................................37
R61503U specification rev.1.1, march 29, 2007, page 2 of 186 instruction ......................................................................................................... 40 instruction data format........................................................................................................ ...................41 index specification/status read/display control instructions .................................................................42 index (ir) .................................................................................................................... ............................................42 status read (sr) ............................................................................................................... .......................................42 start oscillation (r00h) ....................................................................................................... ..................................42 driver output control (r01h)................................................................................................... .............................43 lcd driving wave control (r02h) ................................................................................................ .......................43 entry mode (r03h) .............................................................................................................. ...................................44 display control 1 (r07h) ....................................................................................................... ................................48 display control 2 (r08h) ....................................................................................................... ................................50 note on setting bp and fp...................................................................................................... ...............................50 display control 3 (r09h) ....................................................................................................... ................................52 external display interface control 1 (r0ch).................................................................................... ....................54 external display interface control 2 (r0fh) .................................................................................... ....................57 power control.................................................................................................................. ......................58 power control 1/2 (r10h/r11h) .................................................................................................. ..........................58 power control 3/4 (r12h/r13h) .................................................................................................. ..........................61 power sequence control 5 (r14h)................................................................................................ .........................64 power control 6 (r18h) ......................................................................................................... ................................65 ram access instruction......................................................................................................... ...............66 ram address set horizontal address (r20h), ram address set vertical address (r21h)................................66 write/read ram data ............................................................................................................ ...............67 write data to gram (r22h)...................................................................................................... ............................67 ram access via rgb interface and sy stem interface .............................................................................. .............69 read data from gram (r22h) ..................................................................................................... .........................70 nv memory read data 1/2/3 (r28h/r29h/r2ah) ..................................................................................... ............71 control instruction ........................................................................................................... ...................72 control (1) ~ (9) (r30h ~ r3ah) ............................................................................................... ..........................72 window address control instruction ............................................................................................. .......73 window horizontal ram start address (r50h), window horizontal ram end address (r51h) .......................73 window vertical ram start address (r52h), window vertical ram end address (r52h), ...............................73 base image display control instruction......................................................................................... .......74 driver output control (r70h), base image display co ntrol (r71h), vertical sc roll control (r7ah), ..............74 partial control instruction.................................................................................................... ...................77 partial image 1 display position (r80h) ........................................................................................ ........................77 partial image 1 ram start address (r81h), partia l image 1 ram end addr ess (r82h) ......................................77 partial image 2 display position (r83h) ........................................................................................ ........................77 partial image 2 ram address (r84h), partial image 2 ram end address (r85h), .............................................77 panel interface control instruction ............................................................................................ .............78 panel interface control 1 (r90h)............................................................................................... .............................78 panel interface control 2 (r91h)............................................................................................... .............................79 panel interface control 3 (r92h)............................................................................................... .............................80 panel interface control 4 (r93h)............................................................................................... .............................81 panel interface control 5 (r94h)............................................................................................... .............................82 panel interface control 6 (r95h)............................................................................................... .............................83 nv memory control.............................................................................................................. ................84 nv memory access control 1 (ra0h), nv memory access control 2 (ra1h).....................................................84
R61503U specification rev.1.1, march 29, 2007, page 3 of 186 calibration control (ra4h) ..................................................................................................... ..............................84 instruction list .................................................................................................... 86 reset function .................................................................................................... 88 interface and data format .................................................................................... 90 system interface.................................................................................................. 93 80-system 18-bit interface ..................................................................................................... ................94 80-system 16-bit interface ..................................................................................................... ................95 80-system 9-bit interface ...................................................................................................... .................98 80-system 8-bit interface ...................................................................................................... .................100 serial interface............................................................................................................... ........................104 vsync interface................................................................................................ 107 notes to vsync interface operation ............................................................................................. ......109 external display interface .................................................................................. 111 rgb interface.................................................................................................................. ......................111 enable signal function......................................................................................................... ..............112 rgb interface timing........................................................................................................... ..................113 ram access via system interface in rgb interface operation ..............................................................115 6-bit rgb interface ............................................................................................................ ...................117 data transfer synchronization in 6-bit rgb interface operation............................................................118 16-bit rgb interface........................................................................................................... ...................119 18-bit rgb interface........................................................................................................... ...................120 notes to external display interface operation.................................................................................. .......121 ram address and display position on the panel .............................................. 123 restrictions in setting display control instruction ............................................................................ ......124 instruction setting example.................................................................................................... ................126 high-speed ram write function ...................................................................... 128 notes to high-speed ram write function ......................................................................................... .....129 high-speed ram data write in a window address area .........................................................................130 window address function ................................................................................. 131 scan mode setting .............................................................................................. 132 8-color display mode ......................................................................................... 134 n-line inversion ac drive .................................................................................. 135 alternating timing.............................................................................................. 136 frame-frequency adjustment function ............................................................. 137
R61503U specification rev.1.1, march 29, 2007, page 4 of 186 relationship between liquid crystal drive duty and frame frequency ....................................................137 partial display function ..................................................................................... 138 low power consumption drive settings .............................................................. 139 lcd panel interface timing ................................................................................ 141 internal clock operation ....................................................................................................... ..................141 rgb interface signals .......................................................................................................... ..................142 oscillator ......................................................................................................... 143 correction function .......................................................................................... 144 grayscale amplifier unit ....................................................................................................... .................145 correction registers .......................................................................................................... ...................147 reference voltage generating block (ladder re sistor units and 8-to-1 selectors)...................................148 variable resistors ............................................................................................................. ......................148 ram data (rgb dot data bits) and the source output level.............................................................154 power supply generating circuit ....................................................................... 155 power supply circuit connection exam ple1 (vci1=vciout) ................................................................155 specifications of external elements for th e power supply circuit ....................... 156 voltage generation diagram................................................................................ 157 power supply setting sequence .......................................................................... 159 instruction setting............................................................................................... 160 display on/off................................................................................................................. ...................160 sleep/standby mode............................................................................................................. .................161 deep standby mode .............................................................................................................. ................162 nv memory control........................................................................................... 165 nv memory write/read sequences................................................................................................. .....167 recommended resistance/connection example................................................ 168 absolute maximum ratings ............................................................................... 169 electrical characteristics .................................................................................... 170 dc characteristics ............................................................................................................. ....................170 step-up circuit characteristics ................................................................................................ ...............171 ac characteristics ............................................................................................................. ....................171 80-system bus interface timing characteristics (18/16-bit i/f)............................................................172 80-system bus interface timing characteristics (9/8-bit i/f)................................................................173 serial interface timing characteristics........................................................................................ ..........173 reset timing characteristics ................................................................................................... ..............174
R61503U specification rev.1.1, march 29, 2007, page 5 of 186 rgb interface timing characteristics........................................................................................... ..........174 lcd driver output characteristics .............................................................................................. ...........175 notes to electrical characteristics ............................................................................................ .............176 test circuits.................................................................................................................. .........................180 timing characteristics......................................................................................................... ..................181 80-system bus interface........................................................................................................ ..................................181 clock synchronous serial interface ............................................................................................. ...........................182 reset operation ................................................................................................................ .......................................182 rgb interface .................................................................................................................. .......................................183 lcd driver output .............................................................................................................. ....................................183
R61503U specification rev.1.1, march 29, 2007, page 6 of 186 description the R61503U is a one-chip controller driver lsi for 262,144-color tft panel, incorporating ram for a maximum 176rgb x 220-dot graphics display and 528-channel source driver. the R61503U provides a one-chip solution to drive tft panel by generating gate drive signal and liquid crystal drive power supply. to transfer data efficiently, the R61503U supports high-speed interface via 8-/9-/16-/18-bit port as system interface to microcomputer and high-speed ram write function. as moving picture interface, the R61503U supports rgb interface (vsync, hsync, dotclk, enable, db17-0) via 18-/16-/6-bit port and vsync interface (system interface + vsync). the moving picture interface enables moving picture display at the arbitrary position determined by window address setting. the window address setting enables displaying a moving picture and the data written in the internal ram simultaneously and allows transferring moving picture data not constrained by the position of still picture display. by writing moving picture data via moving picture interface in the window address area, the number of data transfer can be minimized and the power consumption by the system can be reduced. the R61503U can operate at low voltage up to 1.65v for the power supply to the i/o interface unit and it incorporates a voltage follower circuit to generate liquid crystal drive voltage. the R61503U?s power management functions such as 8-color display and deep standby and so on make this lsi an ideal driver for the medium or small sized portable products such as digital cellular phones and small pdas, where long battery life is a major concern.
R61503U specification rev.1.1, march 29, 2007, page 7 of 186 features ? one-chip controller driver for 176rgb x 220-dot graphics display in 262,144 colors on tft panel ? one-chip solution for a-si tft panel ? system interface ? high-speed interface via 8-, 9-, 16-, 18-bit parallel ports ? clock synchronous serial interface ? moving picture display interface ? rgb interface (vsync, hsync, dotclk, enable, db17-0) via 6-, 16-, 18-bit ports ? vsync interface (system interface + vsync) ? high-speed ram write function ? window address function to specify a rectangular area in the internal ram to write data ? writes data within a rectangular area on the internal ram via moving picture interface ? reduces data transfer by specifying the area on the ram to rewrite data ? enables displaying the data in the still picture ram area with a moving picture simultaneously ? color display control functions ? -correction function to display in 262k colors ? 1-line unit vertical scroll function ? low -power consumption architecture (allowing direct input of interface i/o power supply) ? deep standby function ? 8-color display function ? partial display function (max. 32,768 colors) ? input power supply voltages: vcc = 2.5v ~ 3.6 v (logic regulator power supply) iovcc = 1.65v ~ 3.6 v (interface i/o power supply) vci = 2.5v ~ 3.3 v (liquid crystal analog circuit power supply) (vci-vcl 6.0v) ? incorporates a liquid crystal drive power supply circuit ? source driver liquid crystal drive/vcom power supply: ddvdh-agnd = 4.5v ~ 6.0v ? gate drive power supply: vgh-vgl 28.0v ? vcom drive (vcom power supply): vcomh = (ddvdh+0.5)v ~ 2.5v vcoml = (vci+0.5)v ~ gnd ? 87,120-byte internal ram ? internal liquid crystal drive circuit: 528-channel source output and 220-channel gate output ? n-line-/frame-inversion liquid crystal drive ? internal oscillator, hardware reset ? reversible source output shift direction ? tft storage capacitor: cst only ? internal nv memory: for user identification code (4 bits) and vcom level adjustment (12 bits)
R61503U specification rev.1.1, march 29, 2007, page 8 of 186 table 1 R61503U?s power supply main specifications no. item R61503U 1 tft data lines 528 output 2 tft gate lines 220 output 3 tft display storage capacitor cst only (common vcom formula) s1~s528 v0 ~ v31 grayscales g1~g220 vgh-vgl 4 liquid crystal drive output vcom vcomh/vcoml iovcc (interface voltage) 1.65v ~ 3.60v power supply to im0/id, im1-3, reset, db17-0, rd, sdi, sdo, wr/scl, rs, cs*, vsync, hsync, dotclk, enable connect to vcc and vci on the fpc when iovcc, vcc and vci are at the same el ectrical potential. vcc (logic regulator power supply) see note 1 2.50v ~ 3.60v connect to iovcc and vci on the fpc when iovcc, vcc and vci are at the same el ectrical potential. vdd(internal logic power supply) see note 2 1.5v 5 input voltage vci (liquid crystal drive power supply) see note 2 2.50v ~ 3.30v connect to iovcc and vcc on the when iovcc, vcc and vci are at the same electrical potential. ddvdh vci1 x 2 vgh vci1 x 6, x 5, x 4 5 internal step-up circuits vgl vci1 x ?2, x -3, x -4, x -5 notes: 1. when the internal logic regulator is used. 2. generated from the internal logic regulator power supply circuit.
R61503U specification rev.1.1, march 29, 2007, page 9 of 186 block diagram iovcc vciout vcc vddtest vrefc vref vcilvl c13+/c13- g1-g220 vgh vgl cs* rs wr scl rd* sdi sdo db0-17 vsync hsync dotcl k enable vmon vgs vci vci1 c11+/c11- ddvdh c21+/c21- c22+/c22- s1-528 osc2 osc1 reset* test1 test2 rgnd gnd a gnd im3-1,im0/id 18 18 18 18 v31-0 vpp1 vpp2 vpp3 vreg1out vcomr vcom vcomh vcoml testa5 write data latch read data latch timing generator bgr circuit control register (cr) index register (ir) system interface -18 bit -16 bit - 9 bit - 8 bit - 8 bit serial cpg internal reference voltage generating circuit internal logic power supply regulator liquid crystal drive level generating ciruict vcom generating circuit address counter graphics ram (gram) 87,120 bytes latch circuit latch circuit m ac drive latch circuit source line drive circuit gamma adjustment circuit grayscale voltage generating circuit scan data generating circuit gate line drive circuit nv memory flm vcl control register (cr) external display interface vsync hsync dotclk enable db17-0 vddout figure 1
R61503U specification rev.1.1, march 29, 2007, page 10 of 186 pin function table 2 interface signal number i/o connect to function when not in use 4 selects mpu interface format. amplitude: iovcc-iognd. when selecting clock synchronous serial interface, im0 pin is used to set the device code id. - im3 im2 im1 im0/id mpu interface format db pins 0 0 0 0 setting disabled - 0 0 0 1 setting disabled - 0 0 1 0 80-system 16-bit interface db17-10, db8-1 0 0 1 1 80-system 8-bit interface db17-10 0 1 0 id clock synchronous serial interface sdi/sdo 0 1 1 * setting disabled - 1 0 0 0 setting disabled - 1 0 0 1 setting disabled - 1 0 1 0 80-system 18-bit interface db17-0 1 0 1 1 80-system 9-bit interface db17-9 1 1 * * setting disabled - im3-1 im0/id i gnd or iovcc cs* 1 i mpu chip select si gnal. amplitude: iovcc-gnd low: the R61503U is selected and accessible high: the R61503U is not selected and not accessible. - rs 1 i mpu register select signal. amplitude: iovcc-gnd low: select index or status register high: select data register iovcc wr*/scl 1 i mpu write strobe signal in 80-system bus interface operation and enables write operation when wr* is low. synchronous clock signal (scl) in serial interface operation. amplitude: iovcc-gnd iovcc rd* 1 i mpu read strobe signal in 80-system bus interface operation and enables read operation when rd* is low. amplitude: iovcc-gnd iovcc sdi 1 i mpu serial data input (sdi) pin in serial interface operation. the data is inputted on the rising edge of the scl signal. when dake = 1, chip select signal is outputted for dma transfer single address mode. in this case, the R61503U becomes accessible when the signal is low and it becomes inaccessible when the signal is high. amplitude: iovcc-gnd gnd or iovcc sdo 1 o mpu serial data output (sdo) pin in se rial interface operation. the data is outputted on the falling edge of the scl signal. amplitude: iovcc-gnd open
R61503U specification rev.1.1, march 29, 2007, page 11 of 186 table 3 interface (continued) signal number i/o connect to function when not in use db0-db17 18 i/o mpu parallel bi-directional data bus for 80-system interface operation (amplitude: iovcc-gnd). fix unused pins to either iovcc or gnd level. 8-bit i/f: db17-db10 are used. 9-bit i/f: db17-db9 are used. 16-bit i/f: db17-db10 and db8-1 are used. 18-bit i/f: db17-db0 are used. parallel bi-directional data bus for rgb interface operation (amplitude: iovcc-gnd). 6-bit i/f: db17-db12 are used. 16-bit i/f: db17-db13 and db11-1 are used. 18-bit i/f: db17-db0 are used. gnd or iovcc enable 1 i mpu data enable signal for rgb interface operation. (amplitude: iovcc-gnd). low: accessible (select) high: note accessible (not select) the polarity of enable signal can be inverted by setting the epl bit. gnd or iovcc vsync 1 i mpu frame synchronous signal for rgb interface operation. low active. (amplitude: iovcc-gnd). gnd or iovcc hsync 1 i mpu line synchronous signal for rgb interface operation. low active. (amplitude: iovcc-gnd). gnd or iovcc dotclk 1 i mpu dot clock signal for rgb interface operation. the data is inputted on the rising edge of dotclk. (amplitude: iovcc-gnd). gnd or iovcc flm 1 o mpu frame head pulse to synchronize ram data write operation with the frame head position. (amplitude: iovcc-gnd). open table 4 reset an d oscillator signal number i/o connect to function when not in use reset* 1 i reset generating circuit reset signal. initializes the R61503U when reset input is low. make sure to execute a power-on reset when turning on the power supply. (amplitude: iovcc-gnd). - osc1 osc2 2 i o oscillator connect an external resistor for rc oscillation. -
R61503U specification rev.1.1, march 29, 2007, page 12 of 186 table 5 power supply signal number i/o connect to function when not in use vcc 1 - power supply power supply to internal logic regulator circuit: vcc = 2.5v~3.6v. vcc iovcc - gnd 1 - power supply internal logic gnd: gnd = 0v. - rgnd 1 - power supply internal ram gnd: rgnd and gnd must be at the same electrical potential. in case of cog, connect to gnd on the fpc to prevent noise. - vdd vddout 1 o stabilizing capacitor internal logic regulator output used for internal logic power supply. connect a stabilizing capacitor. - iovcc 1 - power supply power supply to interface pins: reset; cs; wr; rd; rs; db17-0; vsync; hsync; dotclk; enable. iovcc = 1.65v ~ 3.6v. vcc iovcc in case of cog, connect to vcc on the fpc if iovcc=vcc, to prevent noise. - agnd 1 - power supply analog gnd (for logic regulator and liquid crystal power supply circuit): agnd = 0v. in case of cog, connect to gnd on the fpc to prevent noise. - vci 1 i power supply power supply to liquid crystal power supply analog circuit. connect to an external power supply of 2.5v ~ 3.3v. - vcilvl 1 i reference power supply vcilvl and vci must be at the same electrical potential. connect vcilvl to an external power supply of 2.5v ~ 3.3v. in case of cog, connect to vci on the fpc to prevent noise. - vpp1 1 i power supply or open internal nv memory power supply. apply the following voltages on vpp1 ~ vpp3 respectively according to the power supply on sequence. open operation mode vpp1 vp2 vpp3 vpp2 1 i power supply or open nv memory write 9.00.3v 7.50.3v gnd open nv memory read open open open vpp3 1 i power supply or open open
R61503U specification rev.1.1, march 29, 2007, page 13 of 186 table 6 step-up circuit signal number i/o connect to function when not in use vci1 1 i/o vciout internal reference voltage generated between vci and gnd. the output voltage level is set by instruction (vc). reference voltage for step-up circuit 1. vci1 must be set so that the output voltages ddvdh, vgh, vgl are generated within the respective setting ranges. - ddvdh 1 o stabilizing capacitor ddvdh is generated from vci1 x 2 in the step-up circuit 1. the step-up factor is set by instruction (bt). ddvdh = 4.5v ~ 6.0v liquid crystal power supply for source driver. - vgh 1 o stabilizing capacitor, lcd panel liquid crystal drive power supply generated from vci1 and ddvdh in the step-up circuit 2 (see note below). the step-up factor is set by instruction (bt). - vgl 1 o stabilizing capacitor, lcd panel liquid crystal drive power supply generated from vci1 and ddvdh in the step-up circuit 2 (see note below). the step-up factor is set by instruction (bt). - c11+, c11 2 i o step-up capacitor capacitor connection pins of the step-up circuit 1. - c13+, c13- c21+, c21- c22+, c22- 6 i o step-up capacitor capacitor connection pins of the step-up circuit 2. - vcl 1 o stabilizing capacitor power supply for vcoml drive. - note: make sure vgh-vgl amplitude = max. 28v.
R61503U specification rev.1.1, march 29, 2007, page 14 of 186 table 7 liquid crystal drive signal number i/o connect to function when not in use vreg1 out 1 o stabilizing capacitor vreg1out is generated from vcilvl and the output level is set by instruction (vrh) and used for (1) source driver grayscale voltage vdh, (2) vcomh level reference voltage, and (3) vcom amplitude reference voltage. connect to a stabilizing capacitor when it is in use. vreg1out = 3.5v ~ (ddvdh ? 0.5)v open vcom 1 o tft common electrode power supply to tft common electrode. the vcom amplitude is determined by vcomh and vcoml levels. the alternating cycle can be set to line cycle or frame cycle. also halting/starting vcom output can be controlled by instruction (von). open vcomh 1 o stabilizing capacitor the high level of vcom. the vcomh output level can be determined by either internal electronic volume or external variable resistor (vcomr). open vcoml 1 o stabilizing capacitor the low level of vcom. open vcomr 1 i variable resistor or open connect a variable resistor between vreg1out and gnd when adjusting the vcomh level externally. open vgs 1 i gnd reference level of gr ayscale voltage generating circuit. - s1~s528 528 o lcd liquid crystal application vo ltage. to change the shift direction of segment signal output, set the ss bit as follows. when ss = 0, the data in the ram address h00000 is output from s1. when ss = 1, the data in the ram address h00000 is output from s528. open g1~g220 220 o lcd gate output signal gate select level: vgh gate non-select level: vgl open
R61503U specification rev.1.1, march 29, 2007, page 15 of 186 table 8 liquid crystal drive signal number i/o connect to function when not in use vrefc 1 i agnd test pin. fix it to gnd level. - vref 1 o open test pin. leave it open. open vddtest 1 i agnd test pin. fix it to gnd level. - testa5 o open test pin. leave it open. open iovccdum1, iovccdum2 2 o - use when fixing the electrical potential of unused interface pins and fixed pins (iovcc output). when not in use, leave it open. open gnddum1, gnddum2 2 o - use when fixing the electrical potential of unused interface pins and fixed pins (gnd output). when not in use, leave it open. open dummy 1-8 8 - - dummy pads. leave them open. open vgldmy 1-4 4 o - dummy pads. leave them open. open testo 1-15 32 o - dummy pads. leave them open. open exdum1-4 1 - - leave them open. open test1-2 1 i gnd test pins. connect to gnd. gnd patents of dummy pin which is used to fix pin to vcc or gnd are pending and granted. patent issued: united states patent no. 6,323,930 patent pending: japanese application no. 10-514484 korean application no. 19997002322 taiwanese application no.086103756 (pct/jp96/02728(w098/12597)
R61503U pad arrangement rev0.0 2006.06.08 1 testo1 2 vpp1 dummy8 968 3 vpp1 dummy7 967 4 vpp1 vgldmy4 966 5 vpp1 g1 965 6 vpp2 g3 964 7 vpp2 g5 963 8 vpp2 g7 962 9 vpp2 g9 961 10 vpp2 11 vpp2 12 vpp3 13 vpp3 14 vpp3 15 vpp3 16 vpp3 17 vpp3 18 iognddum1 19 test1 20 test2 21 im0/id 22 im1 23 im2 24 im3 25 iovccdum1 26 reset* 27 vsync 28 hsync 29 dotclk 30 enable 31 db17 32 db16 33 db15 g211 860 34 db14 g213 859 35 db13 g215 858 36 db12 g217 857 37 db11 g219 856 38 db10 vgldmy3 855 39 db9 dummy6 854 40 db8 41 iognddum2 42 db7 43 db6 44 db5 45 db4 46 db3 dummy5 853 47 db2 s1 852 48 db1 s2 851 49 db0 s3 850 50 sdo s4 849 51 sdi s5 848 52 rd* s6 847 53 wr*/scl s7 846 54 rs s8 845 55 cs* 56 exdum1 57 exdum2 58 exdum3 59 exdum4 60 flm 61 iovccdum2 62 osc1 63 testo2 64 testo3 65 osc2 66 testo4 67 vref 68 vrefc 69 vddtest 70 iovcc 71 iovcc 72 iovcc 73 vcc 74 vcc 75 vcc 76 vcc 77 vcc 78 vddout 79 vddout 80 vddout 81 vddout 82 vdd 83 vdd 84 vdd 85 vdd 86 vdd 87 vdd 88 vdd 89 vdd 90 vdd 91 vdd 92 vdd 93 vdd 94 gnd 95 gnd 96 gnd 97 gnd 98 gnd 99 gnd 100 gnd 101 gnd 102 rgnd 103 rgnd 104 rgnd 105 rgnd 106 rgnd 107 rgnd 108 rgnd 109 rgnd 110 rgnd 111 rgnd 112 rgnd 113 rgnd 114 agnd 115 agnd 116 agnd 117 agnd 118 agnd 119 agnd 120 agnd 121 agnd 122 vgs 123 ddvdh 124 ddvdh 125 ddvdh 126 ddvdh 127 ddvdh 128 ddvdh 129 c11m 130 c11m 131 c11m 132 c11m 133 c11p 134 c11p 135 c11p 136 c11p 137 vci1 138 vci1 139 vci1 140 vci1 141 vci1 142 vci1 143 vci1 144 vci1 145 vci 146 vci 147 vci 148 vci 149 vci 150 vci 151 vcilvl 152 testo5 153 c13p 154 c13p 155 c13p 156 c13p 157 c13m 158 c13m 159 c13m 160 c13m 161 c22m s524 329 162 c22m s525 328 163 c22p s526 327 164 c22p s527 326 165 c21m s528 325 166 c21m dummy4 324 167 c21p 168 c21p 169 testo6 170 testo7 171 vgh dummy3 323 172 vgh vgldmy2 322 173 vgh g220 321 174 vgh g218 320 175 vgh g216 319 176 vgh g214 318 177 testo8 g212 317 178 testo9 179 vgl 180 vgl 181 vgl 182 vgl 183 vgl 184 vgl 185 vgl 186 testo10 187 testo11 188 vreg1out 189 testa5 190 vcomr 191 vcl 192 vcl 193 vcl 194 vcl 195 vcoml 196 vcoml 197 vcoml 198 vcoml 199 vcom 200 vcom 201 vcom 202 vcom g10 216 203 vcom g8 215 204 vcomh g6 214 205 vcomh g4 213 206 vcomh g2 212 207 vcomh vgldmy1 211 208 testo12 dummy2 210 dummy1 209 R61503U staggered arrangement top view (bump view) 228um 228um chip bump top view (1-a) (2-a) (1-b) (2-b)
R61503U specification rev.1.1, march 29, 2007, page 17 of 186 chip size a b c d e f g h i j a b type a type b chip size: 15.20 mm x 1.07 mm chip thickness: 280 m (typ.) pad coordinates: pad center pad origin: chip center au bump size: (1) 50 m x 80 m no.1 ~ no.208 (2) 19 m x 110 m no.209 ~ no.968 au bump pitch: see pad coordinates. au bump height: 15m (typ.) no. in the figure corresponds to no. in pad coordinate table. 1-a type a type a type b type b alignment mark 1-b 2-a 2-b -7465 7465 -7500 7500 -400 400 -293 293 y x alignment mark unit ( m) a: 30 b: 30 c: 30 d: 30 e: 30 f: 30 g: 150 h: 150 i: 20 j: 20 unit ( m) a: 70 b: 53 non-pattern area figure 2
R61503U pad coordinates (no.1) (unit: m 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 1 testo1 -7245 -430 51 sdi -3745 -430 2 vpp1 -7175 -430 52 rd* -3675 -430 3 vpp1 -7105 -430 53 wr*/scl -3605 -430 4 vpp1 -7035 -430 54 rs -3535 -430 5 vpp1 -6965 -430 55 cs* -3465 -430 6 vpp2 -6895 -430 56 exdum1 -3395 -430 7 vpp2 -6825 -430 57 exdum2 -3325 -430 8 vpp2 -6755 -430 58 exdum3 -3255 -430 9 vpp2 -6685 -430 59 exdum4 -3185 -430 10 vpp2 -6615 -430 60 flm -3115 -430 11 vpp2 -6545 -430 61 iovccdum2 -3045 -430 12 vpp3 -6475 -430 62 osc1 -2975 -430 13 vpp3 -6405 -430 63 testo2 -2905 -430 14 vpp3 -6335 -430 64 testo3 -2835 -430 15 vpp3 -6265 -430 65 osc2 -2765 -430 16 vpp3 -6195 -430 66 testo4 -2695 -430 17 vpp3 -6125 -430 67 vref -2625 -430 18 iognddum1 -6055 -430 68 vrefc -2555 -430 19 test1 -5985 -430 69 vddtest -2485 -430 20 test2 -5915 -430 70 iovcc -2415 -430 21 im0/id -5845 -430 71 iovcc -2345 -430 22 im1 -5775 -430 72 iovcc -2275 -430 23 im2 -5705 -430 73 vcc -2205 -430 24 im3 -5635 -430 74 vcc -2135 -430 25 iovccdum1 -5565 -430 75 vcc -2065 -430 26 reset* -5495 -430 76 vcc -1995 -430 27 vsync -5425 -430 77 vcc -1925 -430 28 hsync -5355 -430 78 vddout -1855 -430 29 dotclk -5285 -430 79 vddout -1785 -430 30 enable -5215 -430 80 vddout -1715 -430 31 db17 -5145 -430 81 vddout -1645 -430 32 db16 -5075 -430 82 vdd -1575 -430 33 db15 -5005 -430 83 vdd -1505 -430 34 db14 -4935 -430 84 vdd -1435 -430 35 db13 -4865 -430 85 vdd -1365 -430 36 db12 -4795 -430 86 vdd -1295 -430 37 db11 -4725 -430 87 vdd -1225 -430 38 db10 -4655 -430 88 vdd -1155 -430 39 db9 -4585 -430 89 vdd -1085 -430 40 db8 -4515 -430 90 vdd -1015 -430 41 iognddum2 -4445 -430 91 vdd -945 -430 42 db7 -4375 -430 92 vdd -875 -430 43 db6 -4305 -430 93 vdd -805 -430 44 db5 -4235 -430 94 gnd -735 -430 45 db4 -4165 -430 95 gnd -665 -430 46 db3 -4095 -430 96 gnd -595 -430 47 db2 -4025 -430 97 gnd -525 -430 48 db1 -3955 -430 98 gnd -455 -430 49 db0 -3885 -430 99 gnd -385 -430 50 sdo -3815 -430 100 gnd -315 -430
R61503U pad coordinates (no.2) (unit: m 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 101 gnd -245 -430 151 vcilvl 3255 -430 102 rgnd -175 -430 152 testo5 3325 -430 103 rgnd -105 -430 153 c13p 3395 -430 104 rgnd -35 -430 154 c13p 3465 -430 105 rgnd 35 -430 155 c13p 3535 -430 106 rgnd 105 -430 156 c13p 3605 -430 107 rgnd 175 -430 157 c13m 3675 -430 108 rgnd 245 -430 158 c13m 3745 -430 109 rgnd 315 -430 159 c13m 3815 -430 110 rgnd 385 -430 160 c13m 3885 -430 111 rgnd 455 -430 161 c22m 3955 -430 112 rgnd 525 -430 162 c22m 4025 -430 113 rgnd 595 -430 163 c22p 4095 -430 114 agnd 665 -430 164 c22p 4165 -430 115 agnd 735 -430 165 c21m 4235 -430 116 agnd 805 -430 166 c21m 4305 -430 117 agnd 875 -430 167 c21p 4375 -430 118 agnd 945 -430 168 c21p 4445 -430 119 agnd 1015 -430 169 testo6 4515 -430 120 agnd 1085 -430 170 testo7 4585 -430 121 agnd 1155 -430 171 vgh 4655 -430 122 vgs 1225 -430 172 vgh 4725 -430 123 ddvdh 1295 -430 173 vgh 4795 -430 124 ddvdh 1365 -430 174 vgh 4865 -430 125 ddvdh 1435 -430 175 vgh 4935 -430 126 ddvdh 1505 -430 176 vgh 5005 -430 127 ddvdh 1575 -430 177 testo8 5075 -430 128 ddvdh 1645 -430 178 testo9 5145 -430 129 c11m 1715 -430 179 vgl 5215 -430 130 c11m 1785 -430 180 vgl 5285 -430 131 c11m 1855 -430 181 vgl 5355 -430 132 c11m 1925 -430 182 vgl 5425 -430 133 c11p 1995 -430 183 vgl 5495 -430 134 c11p 2065 -430 184 vgl 5565 -430 135 c11p 2135 -430 185 vgl 5635 -430 136 c11p 2205 -430 186 testo10 5705 -430 137 vci1 2275 -430 187 testo11 5775 -430 138 vci1 2345 -430 188 vreg1out 5845 -430 139 vci1 2415 -430 189 testa5 5915 -430 140 vci1 2485 -430 190 vcomr 5985 -430 141 vci1 2555 -430 191 vcl 6055 -430 142 vci1 2625 -430 192 vcl 6125 -430 143 vci1 2695 -430 193 vcl 6195 -430 144 vci1 2765 -430 194 vcl 6265 -430 145 vci 2835 -430 195 vcoml 6335 -430 146 vci 2905 -430 196 vcoml 6405 -430 147 vci 2975 -430 197 vcoml 6475 -430 148 vci 3045 -430 198 vcoml 6545 -430 149 vci 3115 -430 199 vcom 6615 -430 150 vci 3185 -430 200 vcom 6685 -430
R61503U pad coordinates (no.3) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 201 vcom 6755 -430 251 g80 6631 278 202 vcom 6825 -430 252 g82 6612 413 203 vcom 6895 -430 253 g84 6593 278 204 vcomh 6965 -430 254 g86 6574 413 205 vcomh 7035 -430 255 g88 6555 278 206 vcomh 7105 -430 256 g90 6536 413 207 vcomh 7175 -430 257 g92 6517 278 208 testo12 7245 -430 258 g94 6498 413 209 dummy1 7429 278 259 g96 6479 278 210 dummy2 7410 413 260 g98 6460 413 211 vgldmy1 7391 278 261 g100 6441 278 212 g2 7372 413 262 g102 6422 413 213 g4 7353 278 263 g104 6403 278 214 g6 7334 413 264 g106 6384 413 215 g8 7315 278 265 g108 6365 278 216 g10 7296 413 266 g110 6346 413 217 g12 7277 278 267 g112 6327 278 218 g14 7258 413 268 g114 6308 413 219 g16 7239 278 269 g116 6289 278 220 g18 7220 413 270 g118 6270 413 221 g20 7201 278 271 g120 6251 278 222 g22 7182 413 272 g122 6232 413 223 g24 7163 278 273 g124 6213 278 224 g26 7144 413 274 g126 6194 413 225 g28 7125 278 275 g128 6175 278 226 g30 7106 413 276 g130 6156 413 227 g32 7087 278 277 g132 6137 278 228 g34 7068 413 278 g134 6118 413 229 g36 7049 278 279 g136 6099 278 230 g38 7030 413 280 g138 6080 413 231 g40 7011 278 281 g140 6061 278 232 g42 6992 413 282 g142 6042 413 233 g44 6973 278 283 g144 6023 278 234 g46 6954 413 284 g146 6004 413 235 g48 6935 278 285 g148 5985 278 236 g50 6916 413 286 g150 5966 413 237 g52 6897 278 287 g152 5947 278 238 g54 6878 413 288 g154 5928 413 239 g56 6859 278 289 g156 5909 278 240 g58 6840 413 290 g158 5890 413 241 g60 6821 278 291 g160 5871 278 242 g62 6802 413 292 g162 5852 413 243 g64 6783 278 293 g164 5833 278 244 g66 6764 413 294 g166 5814 413 245 g68 6745 278 295 g168 5795 278 246 g70 6726 413 296 g170 5776 413 247 g72 6707 278 297 g172 5757 278 248 g74 6688 413 298 g174 5738 413 249 g76 6669 278 299 g176 5719 278 250 g78 6650 413 300 g178 5700 413
R61503U pad coordinates (no.4) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 301 g180 5681 278 351 s502 4522 413 302 g182 5662 413 352 s501 4503 278 303 g184 5643 278 353 s500 4484 413 304 g186 5624 413 354 s499 4465 278 305 g188 5605 278 355 s498 4446 413 306 g190 5586 413 356 s497 4427 278 307 g192 5567 278 357 s496 4408 413 308 g194 5548 413 358 s495 4389 278 309 g196 5529 278 359 s494 4370 413 310 g198 5510 413 360 s493 4351 278 311 g200 5491 278 361 s492 4332 413 312 g202 5472 413 362 s491 4313 278 313 g204 5453 278 363 s490 4294 413 314 g206 5434 413 364 s489 4275 278 315 g208 5415 278 365 s488 4256 413 316 g210 5396 413 366 s487 4237 278 317 g212 5377 278 367 s486 4218 413 318 g214 5358 413 368 s485 4199 278 319 g216 5339 278 369 s484 4180 413 320 g218 5320 413 370 s483 4161 278 321 g220 5301 278 371 s482 4142 413 322 vgldmy2 5282 413 372 s481 4123 278 323 dummy3 5263 278 373 s480 4104 413 324 dummy4 5035 278 374 s479 4085 278 325 s528 5016 413 375 s478 4066 413 326 s527 4997 278 376 s477 4047 278 327 s526 4978 413 377 s476 4028 413 328 s525 4959 278 378 s475 4009 278 329 s524 4940 413 379 s474 3990 413 330 s523 4921 278 380 s473 3971 278 331 s522 4902 413 381 s472 3952 413 332 s521 4883 278 382 s471 3933 278 333 s520 4864 413 383 s470 3914 413 334 s519 4845 278 384 s469 3895 278 335 s518 4826 413 385 s468 3876 413 336 s517 4807 278 386 s467 3857 278 337 s516 4788 413 387 s466 3838 413 338 s515 4769 278 388 s465 3819 278 339 s514 4750 413 389 s464 3800 413 340 s513 4731 278 390 s463 3781 278 341 s512 4712 413 391 s462 3762 413 342 s511 4693 278 392 s461 3743 278 343 s510 4674 413 393 s460 3724 413 344 s509 4655 278 394 s459 3705 278 345 s508 4636 413 395 s458 3686 413 346 s507 4617 278 396 s457 3667 278 347 s506 4598 413 397 s456 3648 413 348 s505 4579 278 398 s455 3629 278 349 s504 4560 413 399 s454 3610 413 350 s503 4541 278 400 s453 3591 278
R61503U pad coordinates (no.5) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 401 s452 3572 413 451 s402 2622 413 402 s451 3553 278 452 s401 2603 278 403 s450 3534 413 453 s400 2584 413 404 s449 3515 278 454 s399 2565 278 405 s448 3496 413 455 s398 2546 413 406 s447 3477 278 456 s397 2527 278 407 s446 3458 413 457 s396 2508 413 408 s445 3439 278 458 s395 2489 278 409 s444 3420 413 459 s394 2470 413 410 s443 3401 278 460 s393 2451 278 411 s442 3382 413 461 s392 2432 413 412 s441 3363 278 462 s391 2413 278 413 s440 3344 413 463 s390 2394 413 414 s439 3325 278 464 s389 2375 278 415 s438 3306 413 465 s388 2356 413 416 s437 3287 278 466 s387 2337 278 417 s436 3268 413 467 s386 2318 413 418 s435 3249 278 468 s385 2299 278 419 s434 3230 413 469 s384 2280 413 420 s433 3211 278 470 s383 2261 278 421 s432 3192 413 471 s382 2242 413 422 s431 3173 278 472 s381 2223 278 423 s430 3154 413 473 s380 2204 413 424 s429 3135 278 474 s379 2185 278 425 s428 3116 413 475 s378 2166 413 426 s427 3097 278 476 s377 2147 278 427 s426 3078 413 477 s376 2128 413 428 s425 3059 278 478 s375 2109 278 429 s424 3040 413 479 s374 2090 413 430 s423 3021 278 480 s373 2071 278 431 s422 3002 413 481 s372 2052 413 432 s421 2983 278 482 s371 2033 278 433 s420 2964 413 483 s370 2014 413 434 s419 2945 278 484 s369 1995 278 435 s418 2926 413 485 s368 1976 413 436 s417 2907 278 486 s367 1957 278 437 s416 2888 413 487 s366 1938 413 438 s415 2869 278 488 s365 1919 278 439 s414 2850 413 489 s364 1900 413 440 s413 2831 278 490 s363 1881 278 441 s412 2812 413 491 s362 1862 413 442 s411 2793 278 492 s361 1843 278 443 s410 2774 413 493 s360 1824 413 444 s409 2755 278 494 s359 1805 278 445 s408 2736 413 495 s358 1786 413 446 s407 2717 278 496 s357 1767 278 447 s406 2698 413 497 s356 1748 413 448 s405 2679 278 498 s355 1729 278 449 s404 2660 413 499 s354 1710 413 450 s403 2641 278 500 s353 1691 278
R61503U pad coordinates (no.6) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 501 s352 1672 413 551 s302 722 413 502 s351 1653 278 552 s301 703 278 503 s350 1634 413 553 s300 684 413 504 s349 1615 278 554 s299 665 278 505 s348 1596 413 555 s298 646 413 506 s347 1577 278 556 s297 627 278 507 s346 1558 413 557 s296 608 413 508 s345 1539 278 558 s295 589 278 509 s344 1520 413 559 s294 570 413 510 s343 1501 278 560 s293 551 278 511 s342 1482 413 561 s292 532 413 512 s341 1463 278 562 s291 513 278 513 s340 1444 413 563 s290 494 413 514 s339 1425 278 564 s289 475 278 515 s338 1406 413 565 s288 456 413 516 s337 1387 278 566 s287 437 278 517 s336 1368 413 567 s286 418 413 518 s335 1349 278 568 s285 399 278 519 s334 1330 413 569 s284 380 413 520 s333 1311 278 570 s283 361 278 521 s332 1292 413 571 s282 342 413 522 s331 1273 278 572 s281 323 278 523 s330 1254 413 573 s280 304 413 524 s329 1235 278 574 s279 285 278 525 s328 1216 413 575 s278 266 413 526 s327 1197 278 576 s277 247 278 527 s326 1178 413 577 s276 228 413 528 s325 1159 278 578 s275 209 278 529 s324 1140 413 579 s274 190 413 530 s323 1121 278 580 s273 171 278 531 s322 1102 413 581 s272 152 413 532 s321 1083 278 582 s271 133 278 533 s320 1064 413 583 s270 114 413 534 s319 1045 278 584 s269 95 278 535 s318 1026 413 585 s268 76 413 536 s317 1007 278 586 s267 57 278 537 s316 988 413 587 s266 38 413 538 s315 969 278 588 s265 19 278 539 s314 950 413 589 s264 -19 278 540 s313 931 278 590 s263 -38 413 541 s312 912 413 591 s262 -57 278 542 s311 893 278 592 s261 -76 413 543 s310 874 413 593 s260 -95 278 544 s309 855 278 594 s259 -114 413 545 s308 836 413 595 s258 -133 278 546 s307 817 278 596 s257 -152 413 547 s306 798 413 597 s256 -171 278 548 s305 779 278 598 s255 -190 413 549 s304 760 413 599 s254 -209 278 550 s303 741 278 600 s253 -228 413
R61503U pad coordinates (no.7) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 601 s252 -247 278 651 s202 -1197 278 602 s251 -266 413 652 s201 -1216 413 603 s250 -285 278 653 s200 -1235 278 604 s249 -304 413 654 s199 -1254 413 605 s248 -323 278 655 s198 -1273 278 606 s247 -342 413 656 s197 -1292 413 607 s246 -361 278 657 s196 -1311 278 608 s245 -380 413 658 s195 -1330 413 609 s244 -399 278 659 s194 -1349 278 610 s243 -418 413 660 s193 -1368 413 611 s242 -437 278 661 s192 -1387 278 612 s241 -456 413 662 s191 -1406 413 613 s240 -475 278 663 s190 -1425 278 614 s239 -494 413 664 s189 -1444 413 615 s238 -513 278 665 s188 -1463 278 616 s237 -532 413 666 s187 -1482 413 617 s236 -551 278 667 s186 -1501 278 618 s235 -570 413 668 s185 -1520 413 619 s234 -589 278 669 s184 -1539 278 620 s233 -608 413 670 s183 -1558 413 621 s232 -627 278 671 s182 -1577 278 622 s231 -646 413 672 s181 -1596 413 623 s230 -665 278 673 s180 -1615 278 624 s229 -684 413 674 s179 -1634 413 625 s228 -703 278 675 s178 -1653 278 626 s227 -722 413 676 s177 -1672 413 627 s226 -741 278 677 s176 -1691 278 628 s225 -760 413 678 s175 -1710 413 629 s224 -779 278 679 s174 -1729 278 630 s223 -798 413 680 s173 -1748 413 631 s222 -817 278 681 s172 -1767 278 632 s221 -836 413 682 s171 -1786 413 633 s220 -855 278 683 s170 -1805 278 634 s219 -874 413 684 s169 -1824 413 635 s218 -893 278 685 s168 -1843 278 636 s217 -912 413 686 s167 -1862 413 637 s216 -931 278 687 s166 -1881 278 638 s215 -950 413 688 s165 -1900 413 639 s214 -969 278 689 s164 -1919 278 640 s213 -988 413 690 s163 -1938 413 641 s212 -1007 278 691 s162 -1957 278 642 s211 -1026 413 692 s161 -1976 413 643 s210 -1045 278 693 s160 -1995 278 644 s209 -1064 413 694 s159 -2014 413 645 s208 -1083 278 695 s158 -2033 278 646 s207 -1102 413 696 s157 -2052 413 647 s206 -1121 278 697 s156 -2071 278 648 s205 -1140 413 698 s155 -2090 413 649 s204 -1159 278 699 s154 -2109 278 650 s203 -1178 413 700 s153 -2128 413
R61503U pad coordinates (no.8) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 701 s152 -2147 278 751 s102 -3097 278 702 s151 -2166 413 752 s101 -3116 413 703 s150 -2185 278 753 s100 -3135 278 704 s149 -2204 413 754 s99 -3154 413 705 s148 -2223 278 755 s98 -3173 278 706 s147 -2242 413 756 s97 -3192 413 707 s146 -2261 278 757 s96 -3211 278 708 s145 -2280 413 758 s95 -3230 413 709 s144 -2299 278 759 s94 -3249 278 710 s143 -2318 413 760 s93 -3268 413 711 s142 -2337 278 761 s92 -3287 278 712 s141 -2356 413 762 s91 -3306 413 713 s140 -2375 278 763 s90 -3325 278 714 s139 -2394 413 764 s89 -3344 413 715 s138 -2413 278 765 s88 -3363 278 716 s137 -2432 413 766 s87 -3382 413 717 s136 -2451 278 767 s86 -3401 278 718 s135 -2470 413 768 s85 -3420 413 719 s134 -2489 278 769 s84 -3439 278 720 s133 -2508 413 770 s83 -3458 413 721 s132 -2527 278 771 s82 -3477 278 722 s131 -2546 413 772 s81 -3496 413 723 s130 -2565 278 773 s80 -3515 278 724 s129 -2584 413 774 s79 -3534 413 725 s128 -2603 278 775 s78 -3553 278 726 s127 -2622 413 776 s77 -3572 413 727 s126 -2641 278 777 s76 -3591 278 728 s125 -2660 413 778 s75 -3610 413 729 s124 -2679 278 779 s74 -3629 278 730 s123 -2698 413 780 s73 -3648 413 731 s122 -2717 278 781 s72 -3667 278 732 s121 -2736 413 782 s71 -3686 413 733 s120 -2755 278 783 s70 -3705 278 734 s119 -2774 413 784 s69 -3724 413 735 s118 -2793 278 785 s68 -3743 278 736 s117 -2812 413 786 s67 -3762 413 737 s116 -2831 278 787 s66 -3781 278 738 s115 -2850 413 788 s65 -3800 413 739 s114 -2869 278 789 s64 -3819 278 740 s113 -2888 413 790 s63 -3838 413 741 s112 -2907 278 791 s62 -3857 278 742 s111 -2926 413 792 s61 -3876 413 743 s110 -2945 278 793 s60 -3895 278 744 s109 -2964 413 794 s59 -3914 413 745 s108 -2983 278 795 s58 -3933 278 746 s107 -3002 413 796 s57 -3952 413 747 s106 -3021 278 797 s56 -3971 278 748 s105 -3040 413 798 s55 -3990 413 749 s104 -3059 278 799 s54 -4009 278 750 s103 -3078 413 800 s53 -4028 413
R61503U pad coordinates (no.9) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 801 s52 -4047 278 851 s2 -4997 278 802 s51 -4066 413 852 s1 -5016 413 803 s50 -4085 278 853 dummy5 -5035 278 804 s49 -4104 413 854 dummy6 -5263 278 805 s48 -4123 278 855 vgldmy3 -5282 413 806 s47 -4142 413 856 g219 -5301 278 807 s46 -4161 278 857 g217 -5320 413 808 s45 -4180 413 858 g215 -5339 278 809 s44 -4199 278 859 g213 -5358 413 810 s43 -4218 413 860 g211 -5377 278 811 s42 -4237 278 861 g209 -5396 413 812 s41 -4256 413 862 g207 -5415 278 813 s40 -4275 278 863 g205 -5434 413 814 s39 -4294 413 864 g203 -5453 278 815 s38 -4313 278 865 g201 -5472 413 816 s37 -4332 413 866 g199 -5491 278 817 s36 -4351 278 867 g197 -5510 413 818 s35 -4370 413 868 g195 -5529 278 819 s34 -4389 278 869 g193 -5548 413 820 s33 -4408 413 870 g191 -5567 278 821 s32 -4427 278 871 g189 -5586 413 822 s31 -4446 413 872 g187 -5605 278 823 s30 -4465 278 873 g185 -5624 413 824 s29 -4484 413 874 g183 -5643 278 825 s28 -4503 278 875 g181 -5662 413 826 s27 -4522 413 876 g179 -5681 278 827 s26 -4541 278 877 g177 -5700 413 828 s25 -4560 413 878 g175 -5719 278 829 s24 -4579 278 879 g173 -5738 413 830 s23 -4598 413 880 g171 -5757 278 831 s22 -4617 278 881 g169 -5776 413 832 s21 -4636 413 882 g167 -5795 278 833 s20 -4655 278 883 g165 -5814 413 834 s19 -4674 413 884 g163 -5833 278 835 s18 -4693 278 885 g161 -5852 413 836 s17 -4712 413 886 g159 -5871 278 837 s16 -4731 278 887 g157 -5890 413 838 s15 -4750 413 888 g155 -5909 278 839 s14 -4769 278 889 g153 -5928 413 840 s13 -4788 413 890 g151 -5947 278 841 s12 -4807 278 891 g149 -5966 413 842 s11 -4826 413 892 g147 -5985 278 843 s10 -4845 278 893 g145 -6004 413 844 s9 -4864 413 894 g143 -6023 278 845 s8 -4883 278 895 g141 -6042 413 846 s7 -4902 413 896 g139 -6061 278 847 s6 -4921 278 897 g137 -6080 413 848 s5 -4940 413 898 g135 -6099 278 849 s4 -4959 278 899 g133 -6118 413 850 s3 -4978 413 900 g131 -6137 278
R61503U pad coordinates (no.10) (unit: m) 2006.6.8 rev0.0 pad no pad name x y pad no pad name x y 901 g129 -6156 413 951 g29 -7106 413 902 g127 -6175 278 952 g27 -7125 278 903 g125 -6194 413 953 g25 -7144 413 904 g123 -6213 278 954 g23 -7163 278 905 g121 -6232 413 955 g21 -7182 413 906 g119 -6251 278 956 g19 -7201 278 907 g117 -6270 413 957 g17 -7220 413 908 g115 -6289 278 958 g15 -7239 278 909 g113 -6308 413 959 g13 -7258 413 910 g111 -6327 278 960 g11 -7277 278 911 g109 -6346 413 961 g9 -7296 413 912 g107 -6365 278 962 g7 -7315 278 913 g105 -6384 413 963 g5 -7334 413 914 g103 -6403 278 964 g3 -7353 278 915 g101 -6422 413 965 g1 -7372 413 916 g99 -6441 278 966 vgldmy4 -7391 278 917 g97 -6460 413 967 dummy7 -7410 413 918 g95 -6479 278 968 dummy8 -7429 278 919 g93 -6498 413 920 g91 -6517 278 alignment mark x y 921 g89 -6536 413 cross 1-a) -7465 -400 922 g87 -6555 278 (1-b) 7465 -400 923 g85 -6574 413 bump (2-a) -7500 -293 924 g83 -6593 278 (2-b) 7500 -293 925 g81 -6612 413 926 g79 -6631 278 927 g77 -6650 413 928 g75 -6669 278 929 g73 -6688 413 930 g71 -6707 278 931 g69 -6726 413 932 g67 -6745 278 933 g65 -6764 413 934 g63 -6783 278 935 g61 -6802 413 936 g59 -6821 278 937 g57 -6840 413 938 g55 -6859 278 939 g53 -6878 413 940 g51 -6897 278 941 g49 -6916 413 942 g47 -6935 278 943 g45 -6954 413 944 g43 -6973 278 945 g41 -6992 413 946 g39 -7011 278 947 g37 -7030 413 948 g35 -7049 278 949 g33 -7068 413 950 g31 -7087 278
R61503U specification rev.1.1, march 29, 2007, page 28 of 186 bump size s1~ s528 g1~ g220 i/o pins 2 2 s=2090 m s=4000 m 70 50 20 25 110 19 19 80 unit: m figure 3
R61503U specification rev.1.1, march 29, 2007, page 29 of 186 block function 1. system interface the R61503U supports the following system interfaces: 80-system high-speed interface via 8-, 9-, 16-, 18- bit parallel ports and clock synchronous serial interface. the interface is selected by setting the im3-0 pins. the R61503U has 16-bit index register (ir), 18-bit write-data register (wdr), and 18-bit read-data register (rdr). the ir is the register to store index information from control register and the internal gram. the wdr is the register to temporarily store the data to be written to the internal gram. the rdr is the register to temporarily store the data read from the gram. the data from the mpu to be written to the internal gram is first written to the wdr and then automatically written to the internal gram in internal operation. the data is read via the rdr from the internal gram. therefore, invalid data is sent to the data bus when the first read operation from the internal gram is performed. valid data is read out when the second and subsequent read operations are performed. the instruction execution time except starting oscillation takes 0 clock cycle and instructions can be written consecutively. table 9 register selection (80-system 8/9/16/18-bit parallel interface) wr* rd* rs function 0 1 0 write index to ir 1 0 0 read internal status 0 1 1 write to control regi ster/internal gram via wdr 1 0 1 read from the internal gram via rdr table 10 register selection (clock synchronous serial interface) start byte r/w rs function 0 0 write index to ir 1 0 read internal status 0 1 write to control regist er/internal gram via wdr 1 1 read from the internal gram via rdr
R61503U specification rev.1.1, march 29, 2007, page 30 of 186 2. external display interface (rgb, vsync interfaces) the R61503U supports rgb interface and vsync interface as the moving picture display interface (external display interface). when rgb interface is selected, the display operation is synchronized with externally supplied signals, vsync, hsync, and dotclk. in rgb interface operation, data (db17-0) is written in synchronization with these signals according to the polarity of the enable signal (enable) to prevent flicker on display while rewriting display data. in vsync interface operation, the display operation is synchronized with the internal clock and vsync signal, which is used for frame synchronization. the display data is written to the internal gram via system interface but there are restrictions in setting the speed and the method to write data to the internal ram. for details, see the ?external display interface? section. the R61503U allows switching between the external display interface and the system interface by instruction so that the optimal interface is selected for the kind of picture on the panel (still and/or moving picture). the R61503U writes the display data to the internal gram to enable transferring data only when the frame data is updated, which contributes to the reduction of data to be transferred from the system and saving power required for the moving picture display. 3. address counter (ac) the address counter (ac) gives an address to the internal gram. when the address setting instruction is written in the ir, the address information is sent from the ir to the ac. when the data is written to the internal gram, the ac is automatically incremented (plus one) or decremented (minus one). the window address function enables writing data only within the rectangular area specified in gram by setting. 4. graphics ram (gram) gram is graphics ram, which can store a maximum 87,120-byte (176rgb x 220 (dots) x 18(bits)/8) bit pattern data using 18 bits per pixel. 5. grayscale voltage generating circuit the grayscale voltage generating circuit generates liquid crystal drive voltage according to the grayscale data in the -correction registers to enable a maximum 262k-color display. 6. timing generator the timing generator generates timing signals to operate internal circuits such as gram. the R61503U generates timing signals for display operation such as the ram read operation and for internal operation such as ram access from mpu and outputs them separately to avoid mutual interference. also flm is generated internally and output from the timing generator.
R61503U specification rev.1.1, march 29, 2007, page 31 of 186 7. oscillator (osc) the R61503U generates the rc oscillation clock signal by connecting an external oscillation resistor between the osc1 and osc2 pins. the oscillation frequency can be changed by changing the resistance of the external resistor. adjust the oscillation frequency according to operating voltage and frame frequency. in deep standby mode, rc oscillation is halted to reduce power consumption. for details, see ?oscillator?. 8. liquid crystal driver circuit the liquid crystal driver circuit of the R61503U consists of 528-channel source driver (s1 ~ s528) and 220- channel gate driver (g1 ~ g220). the display pattern data is latched when 528 bits of data are input. the latched data control the source driver and generates liquid crystal drive waveform. the shift direction of 528-bit source output from the source driver is determined by instruction (ss bit). the shift direction of gate output from the gate driver can be changed by setting the gs bit. the gate pin assignment can be changed by setting the sm bit. sets sm and gs bits to select the optimal scan mode for the module. 9. internal logic power supply regulator the internal logic power supply regulator generates internal logic power supply vdd. 10. liquid crystal drive power supply circuit the liquid crystal drive power supply circuit generates the voltage levels to drive liquid crystal, vreg1out, ddvdh, vgh, vgl, vcl, and vcom. 11. nv memory 8-bit user identification code and 6-bit vcomh setting instruction are written in nv memory. changing vcomh setting instruction is allowed only once.
R61503U specification rev.1.1, march 29, 2007, page 32 of 186 gram address map relation between gram addresses and positions on the screen (ss= ?0?, bgr= ?0?) table 11 s/g pin s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 ................ s517 s518 s519 s520 s521 s522 s523 s524 s525 s526 s527 s528 gs=0 gs=1 db17-0 db17-0 db17-0 db17-0 ................ db17-0 db17-0 db17-0 db17-0 g1 g220 ?0000?h ?0001?h ?0002?h ?0003?h ......... ?00ac?h ?00ad?h ?00ae?h ?00af?h g2 g219 ?0100?h ?0101?h ?0102?h ?0103?h ......... ?01ac?h ?01ad?h ?01ae?h ?01af?h g3 g218 ?0200?h ?0201?h ?0202?h ?0203?h ......... ?02ac?h ?02ad?h ?02ae?h ?02af?h g4 g217 ?0300?h ?0301?h ?0302?h ?0303?h ......... ?03ac?h ?03ad?h ?03ae?h ?03af?h g5 g216 ?0400?h ?0401?h ?0402?h ?0403?h ......... ?04ac?h ?04ad?h ?04ae?h ?04af?h g6 g215 ?0500?h ?0501?h ?0502?h ?0503?h ......... ?05ac?h ?05ad?h ?05ae?h ?05af?h g7 g214 ?0600?h ?0601?h ?0602?h ?0603?h ......... ?06ac?h ?06ad?h ?06ae?h ?06af?h g8 g213 ?0700?h ?0701?h ?0702?h ?0703?h ......... ?07ac?h ?07ad?h ?07ae?h ?07af?h g9 g212 ?0800?h ?0801?h ?0802?h ?0803?h ......... ?08ac?h ?08ad?h ?08ae?h ?08af?h g10 g211 ?0900?h ?0901?h ?0902?h ?0903?h ......... ?09ac?h ?09ad?h ?09ae?h ?09af?h g11 g210 ?0a00?h ?0a01?h ?0a02?h ?0a03?h ......... ?0aac?h ?0aad?h ?0aae?h ?0aaf?h g12 g209 ?0b00?h ?0b01?h ?0b02?h ?0b03?h ......... ?0bac?h ?0bad?h ?0bae?h ?0baf?h g13 g208 ?0c00?h ?0c01?h ?0c02?h ?0c03?h ......... ?0cac?h ?0cad?h ?0cae?h ?0caf?h g14 g207 ?0d00?h ?0d01?h ?0d02?h ?0d03?h ......... ?0dac?h ?0dad?h ?0dae?h ?0daf?h g15 g206 ?0e00?h ?0e01?h ?0e02?h ?0e03?h ......... ?0eac?h ?0ead?h ?0eae?h ?0eaf?h g16 g205 ?0f00?h ?0f01?h ?0f02?h ?0f03?h ......... ?0fac?h ?0fad?h ?0fae?h ?0faf?h g17 g204 ?1000?h ?1001?h ?1002?h ?1003?h ......... ?10ac?h ?10ad?h ?10ae?h ?10af?h g18 g203 ?1100?h ?1101?h ?1102?h ?1103?h ......... ?11ac?h ?11ad?h ?11ae?h ?11af?h g19 g202 ?1200?h ?1201?h ?1202?h ?1203?h ......... ?12ac?h ?12ad?h ?12ae?h ?12af?h g20 g201 ?1300?h ?1301?h ?1302?h ?1303?h ......... ?13ac?h ?13ad?h ?13ae?h ?13af?h : : : : : : : : : : : : : : : : : : : : g213 g8 ?d400?h ?d401?h ?d402?h ?d403?h ......... ?d4ac?h ?d4ad?h ?d4ae?h ?d4af?h g214 g7 ?d500?h ?d501?h ?d502?h ?d503?h ......... ?d5ac?h ?d5ad?h ?d5ae?h ?d5af?h g215 g6 ?d600?h ?d601?h ?d602?h ?d603?h ......... ?d6ac?h ?d6ad?h ?d6ae?h ?d6af?h g216 g5 ?d700?h ?d701?h ?d702?h ?d703?h ......... ?d7ac?h ?d7ad?h ?d7ae?h ?d7af?h g217 g4 ?d800?h ?d801?h ?d802?h ?d803?h ......... ?d8ac?h ?d8ad?h ?d8ae?h ?d8af?h g218 g3 ?d900?h ?d901?h ?d902?h ?d903?h ......... ?d9ac?h ?d9ad?h ?d9ae?h ?d9af?h g219 g2 ?da00?h ?da01?h ?da02?h ?da03?h ......... ?daac?h ?daad?h ?daae?h ?daaf?h g220 g1 ?db00?h ?db01?h ?db02?h ?db03?h ......... ?dbac?h ?dbad?h ?dbae?h ?dbaf?h
R61503U specification rev.1.1, march 29, 2007, page 33 of 186 relation between gram data and display data (ss= ?0?, bgr= ?0?) the following are the interface formats of the R61503U, showing the relationship between the data written in the gram and the display data (one pixel) in respective interface operations. 80 system 18-bit interface db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) n: lower 8 bits of address (0 ~ 175) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 g3 g2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) 80 system 16 -bit interface n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) 80 system 9-bit interface n: lower 8 bits of address (0 ~ 175) rgb (display data) source outuput gram data rgb (display data) source outuput gram data rgb (display data) source outuput gram data figure 4 80-system interface (ss = ?0?, bgr = ?0?)
R61503U specification rev.1.1, march 29, 2007, page 34 of 186 1st transfer 2nd transfer 3rd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) 80 system 8-bit interface / serial interface (2 transfers/pixel) n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd transfer 3rd tr ansfer db 11 db 10 db 11 db 10 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) n: lower 8 bits of address (0 ~ 175) rgb (display data) source outuput gram data rgb (display data) source outuput gram data rgb (display data) source outuput gram data 80 system 8-bit interface / (3 transfers/pixel (262k-color mode): tri = 1, dfm = 00) 80 system 8-bit interface / (3 transfers/pixel (262k-color mode): tri = 1, dfm = 10) figure 5 80-system interface (ss = ?0?, bgr = ?0?)
R61503U specification rev.1.1, march 29, 2007, page 35 of 186 rgb (display data) source outuput gram data db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 db 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) db 17 db 16 db 15 db 14 db 13 db 11 db 10 db db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) db db db db db db db db db db db db db db db db db db r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(3n+1) s(3n+2) s(3n+3 ) n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd transfer 3rd transfer 6-bit rgb interface 16-bit rgb interface 18 bit rgb interface 7 n: lower 8 bits of address (0 ~ 175) n: lower 8 bits of address (0 ~ 175) rgb (display data) source outuput gram data rgb (display data) source outuput gram data 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 9 figure 6 rgb interface (ss = ?0?, bgr = ?0?)
R61503U specification rev.1.1, march 29, 2007, page 36 of 186 relation between gram address and position on the screen (ss= ?1?, bgr= ?1?) table 12 s/g pin s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 ................ s517 s518 s519 s520 s521 s522 s523 s524 s525 s526 s527 s528 gs=0 gs=1 db17-0 db17-0 db17-0 db17-0 ................ db17-0 db17-0 db17-0 db17-0 g1 g220 ?00af?h ?00ae?h ?00ad?h ?00ac?h ......... ?0003?h ?0002?h ?0001?h ?0000?h g2 g219 ?01af?h ?01ae?h ?01ad?h ?01ac?h ......... ?0103?h ?0102?h ?0101?h ?0100?h g3 g218 ?02af?h ?02ae?h ?02ad?h ?02ac?h ......... ?0203?h ?0202?h ?0201?h ?0200?h g4 g217 ?03af?h ?03ae?h ?03ad?h ?03ac?h ......... ?0303?h ?0302?h ?0301?h ?0300?h g5 g216 ?04af?h ?04ae?h ?04ad?h ?04ac?h ......... ?0403?h ?0402?h ?0401?h ?0400?h g6 g215 ?05af?h ?05ae?h ?05ad?h ?05ac?h ......... ?0503?h ?0502?h ?0501?h ?0500?h g7 g214 ?06af?h ?06ae?h ?06ad?h ?06ac?h ......... ?0603?h ?0602?h ?0601?h ?0600?h g8 g213 ?07af?h ?07ae?h ?07ad?h ?07ac?h ......... ?0703?h ?0702?h ?0701?h ?0700?h g9 g212 ?08af?h ?08ae?h ?08ad?h ?08ac?h ......... ?0803?h ?0802?h ?0801?h ?0800?h g10 g211 ?09af?h ?09ae?h ?09ad?h ?09ac?h ......... ?0903?h ?0902?h ?0901?h ?0900?h g11 g210 ?0aaf?h ?0aae?h ?0aad?h ?0aac?h ......... ?0a03?h ?0a02?h ?0a01?h ?0a00?h g12 g209 ?0baf?h ?0bae?h ?0bad?h ?0bac?h ......... ?0b03?h ?0b02?h ?0b01?h ?0b00?h g13 g208 ?0caf?h ?0cae?h ?0cad?h ?0cac?h ......... ?0c03?h ?0c02?h ?0c01?h ?0c00?h g14 g207 ?0daf?h ?0dae?h ?0dad?h ?0dac?h ......... ?0d03?h ?0d02?h ?0d01?h ?0d00?h g15 g206 ?0eaf?h ?0eae?h ?0ead?h ?0eac?h ......... ?0e03?h ?0e02?h ?0e01?h ?0e00?h g16 g205 ?0faf?h ?0fae?h ?0fad?h ?0fac?h ......... ?0f03?h ?0f02?h ?0f01?h ?0f00?h g17 g204 ?10af?h ?10ae?h ?10ad?h ?10ac?h ......... ?1003?h ?1002?h ?1001?h ?1000?h g18 g203 ?11af?h ?11ae?h ?11ad?h ?11ac?h ......... ?1103?h ?1102?h ?1101?h ?1100?h g19 g202 ?12af?h ?12ae?h ?12ad?h ?12ac?h ......... ?1203?h ?1202?h ?1201?h ?1200?h g20 g201 ?13af?h ?13ae?h ?13ad?h ?13ac?h ......... ?1303?h ?1302?h ?1301?h ?1300?h : : : : : : : : : : : : : : : : : : : : g213 g8 ?d4af?h ?d4ae?h ?d4ad?h ?d4ac ?h ......... ?d403?h ?d402?h ?d401?h ?d400?h g214 g7 ?d5af?h ?d5ae?h ?d5ad?h ?d5ac ?h ......... ?d503?h ?d502?h ?d501?h ?d500?h g215 g6 ?d6af?h ?d6ae?h ?d6ad?h ?d6ac ?h ......... ?d603?h ?d602?h ?d601?h ?d600?h g216 g5 ?d7af?h ?d7ae?h ?d7ad?h ?d7ac ?h ......... ?d703?h ?d702?h ?d701?h ?d700?h g217 g4 ?d8af?h ?d8ae?h ?d8ad?h ?d8ac ?h ......... ?d803?h ?d802?h ?d801?h ?d800?h g218 g3 ?d9af?h ?d9ae?h ?d9ad?h ?d9ac ?h ......... ?d903?h ?d902?h ?d901?h ?d900?h g219 g2 ?daaf?h ?daae?h ?daad?h ?daac?h ......... ?da03?h ?da02?h ?da01?h ?da00?h g220 g1 ?dbaf?h ?dbae?h ?dbad?h ?dbac?h ......... ?db03?h ?db02?h ?db01?h ?db00?h
R61503U specification rev.1.1, march 29, 2007, page 37 of 186 relation between gram data and display data (ss= ?1?, bgr= ?1?) 80 system 18-bit interface db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 s(528 - 3n) s(527 - 3n) s(526 - 3n) n: lower 8 bits of address (0 ~ 175) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 g3 g2 b1 b 0 80 system 16 -bit interface n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 80 system 9-bit interface n: lower 8 bits of address (0 ~ 175) rgb (display data) source outuput gram data rgb (display data) source outuput gram data rgb (display data) source outuput gram data s(528 - 3n) s(527 - 3n) s(526 - 3n) s(528 - 3n) s(527 - 3n) s(526 - 3n) figure 7 80-system interface (ss = ?1?, bgr = ?1?)
R61503U specification rev.1.1, march 29, 2007, page 38 of 186 1st transfer 2nd transfer 3rd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 80 system 8-bit interface / serial interface (2 transfers/pixel) n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd transfer 3rd tr ansfer db 11 db 10 db 11 db 10 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 n: lower 8 bits of address (0 ~ 175) rgb (display data) source outuput gram data rgb (display data) source outuput gram data rgb (display data) source outuput gram data s(528 - 3n) s(527 - 3n) s(526 - 3n) s(528 - 3n) s(527 - 3n) s(526 - 3n) s(528 - 3n) s(527 - 3n) s(526 - 3n) 80 system 8-bit interface / 3 transfers/pixel (262k-color mode): tri = 1, dfm = 00) 80 system 8-bit interface / 3 transfers/pixel (262k-color mode): tri = 1, dfm = 10) figure 8 80-system interface (ss = ?1?, bgr = ?1?)
R61503U specification rev.1.1, march 29, 2007, page 39 of 186 rgb (display data) source outuput gram data db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 db 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 db 17 db 16 db 15 db 14 db 13 db 11 db 10 db db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 db db db db db db db db db db db db db db db db db db r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b 0 n: lower 8 bits of address (0 ~ 175) 1st transfer 2nd transfer 3rd transfer 6-bit rgb interface 16-bit rgb interface 18 bit rgb interface 7 n: lower 8 bits of address (0 ~ 175) n: lower 8 bits of address (0 ~ 175) rgb (display data) source outuput gram data rgb (display data) source outuput gram data s(528 - 3n) s(527 - 3n) s(526 - 3n) s(528 - 3n) s(527 - 3n) s(526 - 3n) s(528 - 3n) s(527 - 3n) s(526 - 3n) 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 9 figure 9 rgb interface (ss = ?1?, bgr = ?1?)
R61503U specification rev.1.1, march 29, 2007, page 40 of 186 instruction the R61503U adopts 18-bit bus architecture to interface to high-performance microcomputer. the R61503U starts internal processing when the control information sent via 18-, 16-, 9-, 8-bit ports is stored in the instruction register (ir) and the data register (dr). since the internal operation of the R61503U is controlled by the signals sent from the microcomputer, register selection signal (rs), read/write signal (r/w), and internal 16-bit data bus signals (ib15 to ib0) are called instruction. the R61503U accesses the internal gram in units of 18 bits. the instructions of the R61503U are categorized into the following 8 groups. 1. index specification 2. status read 3. display control 4. power management control 5. gram address setting 6. transfer data to/from the internal gram 7. -correction 8. nv memory control normally, the instruction to write data in the gram is used the most often. in order to minimize the data transfer and lessen the programming load on the microcomputer, the R61503U rewrites data only within the window address area and updates internal gram address in the address counter automatically as it writes data in the internal gram. the R61503U writes instruction consecutively by executing the instruction within the cycle when it is written (instruction execution time: 0 cycle). as the following figure shows, the data bus used to transfer 16 instruction bits (ib[15:0]) is different according to the interface format. make sure to transfer the instruction bits according to the format of the selected interface.
R61503U specification rev.1.1, march 29, 2007, page 41 of 186 instruction data format the following are detail descriptions of instruction bits (ib15-0). note that the instruction bits ib[15:0] in the following figures are transferred according to the format of the selected interface as shown below. db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 instruction bit (ib) ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 80 system 16-bit interface db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 1st tra nsfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 1st transfer 2nd tr ansfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 80 system 18-bit interface 7 instruction bit (ib) instruction bit (ib) instruction bit (ib) 80 system 9-bit interface 80 system 8-bit interface / serial interface (2/3 transfers) 2nd tr ansfer figure 10 instruction format
R61503U specification rev.1.1, march 29, 2007, page 42 of 186 the following are detail descriptions of instruction bits (ib15-0). note that the instruction bits ib[15:0] in the following figures are transferred according to the format of the selected interface (see figure 10 instruction format). index specification/status read/display control instructions index (ir) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 * * * * * * * * id7 id6 id5 id4 id3 id2 id1 id0 the index register represents the index of the control register to be accessed (r00h ~ rffh) and for ram control using binary numbers from ?0000_0000? to ?1111_1111?. the access to a register and instruction bits in it is prohibited unless the index is specified in the index register. status read (sr) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r 0 0 0 0 0 0 0 0 0 l7 l6 l5 l4 l3 l2 l1 l0 the internal status of the R61503U can be read out from the sr register. l[7:0]: represents the line where the R61503U drives liquid crystal. start oscillation (r00h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 * * * * * * * * * * * * * * * 1 r 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 the start oscillation instruction starts the oscillator from a halt in standby mode. after executing this instruction, wait at least 10 ms to stabilize the oscillator before issuing next instruction. the device code ?1503?h is read out when reading out this register forcibly.
R61503U specification rev.1.1, march 29, 2007, page 43 of 186 driver output control (r01h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 sm 0 ss 0 0 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ss: sets the shift direction of output from the source driver. when ss = ?0?, the source driver output shift from s1 to s528. when ss = ?1?, the source driver output shift from s528 to s1. the combination of ss and bgr settings determines the rgb assignment to the source driver pins s1 ~ s528. when ss = ?0? and bgr = ?0?, rgb dots are assigned one to one from s1 to s528. when ss = ?1? and bgr = ?1?, rgb dots are assigned one to one from s528 to s1. when changing the ss and bgr bits, ram data must be rewritten. sm: sets the gate driver pin arrangement in combination with the gs bit (r70h) to select the optimal scan mode for the module. see ? scan mode setting?. lcd driving wave control (r02h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 1 b/c eor 0 0 0 0 0 0 0 0 default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 eor: by setting eor = ?1?, the polarity of c pattern waveform (one-line inversion waveform) is inverted according to the result of eor (exclusive or) between the odd/even-number frame select signal and the one-line inversion signal. set eor = 1 when the number of lines to drive liquid crystal is not compatible with one-line inversion waveform. for details, see ?one-line inversion ac drive?. b/c: when b/c = ?0?, the liquid crystal drive signal becomes frame-inversion waveform and inverts the polarity of liquid crystal in every frame cycle. when b/c = ?1?, liquid crystal drive signal becomes one- line inversion waveform and inverts the polarity of liquid crystal in every line cycle. for details, see ?line inversion ac drive?.
R61503U specification rev.1.1, march 29, 2007, page 44 of 186 entry mode (r03h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 tri dfm [1] dfm [0] bgr 0 0 hwm 0 0 0 i/d [1] i/d [0] am 0 0 0 default 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 am: sets either horizontal or vertical direction in updating the address counter automatically as the R61503U writes data in the internal gram. am = ?0?, sets the horizontal direction. am = ?1?, sets the vertical direction. when a window address area is specified in gram, the R61503U writes data within the window address area in the direction determined by the i/d1-0, am settings. i/d[1:0]: the ram address is automatically incremented (+1) when i/d = ?1? and decremented (-1) when i/d = ?0? as the R61503U writes data in the gram. the i/d[0] bit sets either increment or decrement of ram address (ad[7:0]) in horizontal direction. the i/d[1] bit sets either increment or decrement decrement of ram address (ad[15:8]) in vertical direction. the am bit sets either horizontal or vertical direction in updating ram address automatically when writing data in the internal ram. hwm: when hwm = ?1?, the R61503U writes data in the internal gram in high speed with low power consumption. in this write operation, the R61503U latches the data in units of horizontal lines of window address area in the line buffer and writes the data line by line at a time in the window address area to minimize the number of ram access and thereby reduce power consumption. when hwm = ?1?, make sure the data is written to the end of the horizontal line within the window address area in each ram write operation. if not, the ram write operation in that line becomes a failure. note 1: dummy write operation is not required in the R61503U?s high speed write operation. note 2: the data in the line buffer is cleared when terminating the ram write operation in the middle of horizontal line and writing other instruction. note 3: when switching from high-speed ram write operation to index write operation, wait at least 2 normal-mode write cycle periods (t cycw ) after writing data in the internal ram. bgr: reverses the order of assigning 18-bit rgb data to the data bus (db17-0) from rgb to bgr. when bgr = 0, the order of rgb dots is not reversed when writing data to the gram. when bgr = 1, the order of rgb dots is reversed when writing data to the gram. dfm[1:0]: sets the interface format when transferring 18-bit data via 80-system 16-/8-bit interface in combination with tri bit. make sure to set dfm[1:0] = ?00?, when not using 16-/8-bit interface. see the figures in the ?system interface? section for details on the interface format in ram write operation.
R61503U specification rev.1.1, march 29, 2007, page 45 of 186 tri: sets the interface format when transferring 18-bit data via 80-system 16-/8-bit interface in combination with dfm[1:0] bits. in 8-bit interface operation, tri =0: 16-bit ram data is transferred in two transfers via 8-bit interface. tri =1: 18-bit ram data is transferred in three transfers via 8-bit interface. in 16-bit interface operation, tri =0: 16-bit ram data is transferred in one-transfer via 16-bit interface. tri =1: 18-bit ram data is transferred in two transfers via 16-bit interface. make sure to set tri = ?0?, when not using 16-/8-bit interface. also, set tri = ?0? in read operation. i/d1-0 = ?00? horizontal: decrement vertical: decrement i/d1-0 = ?01? horizontal: increment vertical: decrement i/d1-0 = ?10? horizontal: decrement vertical: increment i/d1-0 = ?11? horizontal: increment vertical: increment am = ?0? horizontal am = ?1? vertical 0000h dbafh 0000h dbafh 0000h dbafh 0000h dbafh 0000h dbafh 0000h 0000h 0000h dbafh dbafh dbafh figure 11 automatic address transition direction setting (am, i/d[1:0]) note: when a window address area is specified in the gram, the data is written within the window address area.
R61503U specification rev.1.1, march 29, 2007, page 46 of 186 tri dfm 1 dfm 0 0 0 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 0 0 1 0. 1 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 *1) g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 *2) 0 1 1 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 *3) g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 *4) 1 0 b db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1 1 b db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 8- bit interface ram interface format first transfer second transfer 80-system 8-bit interface (2 transfers/pixel) 65,536 colors gram data gram data gram data gram data gram data rgb data rgb data rgb data rgb data rgb data setting disabled 80-system 8-bit interface (2 transfers/pixel) 65,536 colors 80-system 8-bit interface (2 transfers/pixel) 65,536 colors 80-system 8-bit interface (3 transfers/pixel) 262,144 colors 80-system 8-bit interface (3 transfers/pixel) 262,144 colors first transfer second transfer third transfer first transfer second transfer third transfer first transfer second transfer first transfer second transfer notes: *1) the logical product of the upper 5 bits (r5 to r1) is inputted to the lsb data. *2) the logical product of the upper 5 bits (b5 to b1) is inputted to the lsb data. *3) the logical sum of the upper 5 bits (r5 to r1) is inputted to the lsb data. *4) the logical sum of the upper 5 bits (b5 to b1) is inputted to the lsb data. figure 12 8-bit interface ram write interface format
R61503U specification rev.1.1, march 29, 2007, page 47 of 186 tri dfm 1 dfm 0 0 0 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 0 0 1 0. 1 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 *1) g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 *2) 0 1 1 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 *3) g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 *4) 1 0 b db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 17 db 16 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1 1 b db 2 db 1 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 16- bit interface ram interface format setting disabled gram data gram data gram data gram data gram data rgb data rgb data rgb data rgb data rgb data 80-system 16-bit interface (1 transfer/pixel) 65,536 colors 80-system 16-bit interface (1 transfer/pixel) 65,536 colors 80-system 16-bit interface (1 transfer/pixel) 65,536 colors 80-system 16-bit interface (2 transfers/pixel) 262,144 colors 80-system 16-bit interface (2 transfers/pixel) 262,144 colors first transfer second transfer first transfer second transfer first transfer first transfer first transfer notes: *1) the logical product of the upper 5 bits (r5 to r1) is inputted to the lsb data. *2) the logical product of the upper 5 bits (b5 to b1) is inputted to the lsb data. *3) the logical sum of the upper 5 bits (r5 to r1) is inputted to the lsb data. *4) the logical sum of the upper 5 bits (b5 to b1) is inputted to the lsb data. figure 13 16-bit interface ram write interface format
R61503U specification rev.1.1, march 29, 2007, page 48 of 186 display control 1 (r07h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 ptde [1] ptde [0] 0 0 bas ee 0 0 0 gon dte cl 0 d[1] d[0] default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d[1:0]: a graphics display is turned on the panel when writing d1 = ?1?, and is turned off when writing d1 = ?0?. when writing d1 = ?0?, the graphics display data is retained in the internal gram and the R61503U displays the data when writing d1 = ?1?. when d1 = ?0?, i.e. while no display is shown on the panel, all source outputs becomes the gnd level to reduce charging/discharging current, which is generated within the lcd while driving liquid crystal with ac voltage. when the display is turned off by setting d1-0 = 2?b01, the R61503U continues internal display operation. when the display is turned off by setting d1-0 = 2?b00, the R61503U?s internal display operation is halted completely. in combination with the gon, dte setting, the d[1:0] setting controls display on/off. for details, see ? instruction setting ?. table 13 d[1:0] basee ptde source output (s1 ~s528) R61503U?s internal operation 2?h0 * * gnd halt 2?h1 * * gnd operate 2?h2 * * non-lit display level operate 0 0 non-lit display level operate 1 0 base image display operate 0 1 partial image display operate 2?h3 1 1 setting disabled notes: 1. the data write operation from the microcomputer to the internal ram is performed irrespective of the setting of the d[1:0] bits. 2. the internal state of the R61503U in standby mode become the same as when d[1:0] = 2?b00. this does not mean the d[1:0] setting is changed when setting the standby mode. 3. the non-lit display level from the source output pins is determined by instruction (pts). cl: when cl = ?1?, the R61503U enters the 8-color mode. follow the 8-color mode setting sequence when setting the 8-color mode. in 8-color mode, the grayscale amplifiers other than those for the v0 and v31 level are halted. if used in combination with frame-inversion liquid crystal drive, the power consumption will be further reduced.
R61503U specification rev.1.1, march 29, 2007, page 49 of 186 dte, gon: controls the output of liquid crystal panel output signal. table 14 gon dte panel output signal 0 0 vgh 0 1 vgh 1 0 vgl 1 1 vgh/vgl basee: base image display enable bit. when basee = ?0?, no base image is displayed. the R61503U drives liquid crystal at non-lit display level or displays only partial images. when basee = ?1?, the base image is displayed. the d[1:0] setting has precedence over the basee setting. ptde0: partial image 1 enable bit ptde1: partial image 2 enable bit ptde0/1 = 0: turns off partial image. only base image is displayed. ptde0/1 = 1: turns on partial image. set the base image display enable bit to 0 (basee = 0).
R61503U specification rev.1.1, march 29, 2007, page 50 of 186 display control 2 (r08h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 fp [3] fp [2] fp [1] fp [0] 0 0 0 0 bp [3] bp [2] bp [1] bp [0] default 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 fp [3:0]: sets the number of lines for a front porch period (a blank period following the end of display). bp [3:0]: sets the number of lines for a back porch period (a blank period made before the beginning of display). make sure that: bp + fp 16 lines fp 2 lines bp 2 lines in external display interface operation, a back porch (bp) period starts on the falling edge of the vsync signal and the display operation starts after the back porch period. a front porch (fp) starts after the number of display lines set by nl bits is displayed. a blank period will start after a front porch (fp) period and it will continue until next vsync input is detected. note on setting bp and fp set the bp and fp bits as follows in respective operation modes. table 15 bp and fp settings internal clock operation mode bp 2 lines fp 2 lines fp + bp 16 lines rgb interface operation bp 2 lines fp 2 lines fp + bp 16 lines vsync interface operation bp 2 lines fp 2 lines fp + bp = 16 lines
R61503U specification rev.1.1, march 29, 2007, page 51 of 186 table 16 front and back porch period (line periods) fp[3:0] bp[3:0] front and back porch period (line periods) 4?h0 setting inhibited 4?h1 setting inhibited 4?h2 2 lines 4?h3 3 lines 4?h4 4 lines 4?h5 5 lines 4?h6 6 lines 4?h7 7 lines 4?h8 8 lines 4?h9 9 lines 4?ha 10 lines 4?hb 11 lines 4?hc 12 lines 4?hd 13 lines 4?he 14 lines 4?hf setting inhibited back porch front porch vsync note : the output timing to the lcd is delayed by 2 line periods from the input timing of the synchronizing signal. display area figure 14 front, back porch periods
R61503U specification rev.1.1, march 29, 2007, page 52 of 186 display control 3 (r09h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 pts [2] pts [1] pts [0] 0 0 ptg [1] ptg [0] isc [3] isc [2] isc [1] isc [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isc[3:0]: set the scan cycle when ptg[1:0] selects interval scan in non-display area drive period. the scan cycle is defined by n frame periods, where n is an odd number from 3 to 31. the polarity of liquid crystal drive voltage from the gate driver is inverted in the same timing as the interval scan cycle. table 17 isc[3:0] scan cycle time for interval when (fflm) = 60hz isc[3:0] scan cycle time for interval when (fflm) = 60hz 4?h0 0 frame - 4?h8 17 frames 284ms 4?h1 3 frames 50ms 4?h9 19 frames 317ms 4?h2 5 frames 84ms 4?ha 21 frames 351ms 4?h3 7 frames 117ms 4?hb 23 frames 384ms 4?h4 9 frames 150ms 4?hc 25 frames 418ms 4?h5 11 frames 184ms 4?hd 27 frames 451ms 4?h6 13 frames 217ms 4?he 29 frames 484ms 4?h7 15 frames 251ms 4?hf 31 frames 518ms ptg[1:0]: sets the scan mode in non-display area. table 18 ptg[1] ptg[0] scan mode in non- display area source output level in non-display area vcom output 0 0 normal scan pts[2:0] setting ac output 0 1 vgl (fixed) pts[2:0] setting ac output 1 0 interval scan pts[2:0] setting ac output 1 1 setting disabled - -
R61503U specification rev.1.1, march 29, 2007, page 53 of 186 pts[2:0]: sets the source output level in non-display area drive period (front/back porch period and blank area between partial displays). when pts[2] = 1, the operation of amplifiers which generates the grayscales other than v0 and v31 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption. table 19 source output level and voltage genera ting operation in non-display drive period source output level pts[2:0] positive polarity negative polarity grayscale amplifier in operation step-up clock frequency 3?h0 v31 v0 v0 to v31 register setting (dc0, dc1) 3?h1 setting inhibited setting inhibited - - 3?h2 gnd gnd v0 to v31 register setting (dc0, dc1) 3?h3 hi-z hi-z v0 to v31 register setting (dc0, dc1) 3?h4 v31 v0 v0 and v31 1/2 the frequency set by dc0, dc1 3?h5 setting inhibited setting inhibited - - 3?h6 gnd gnd v0 and v31 1/2 the frequency set by dc0, dc1 3?h7 hi-z hi-z v0 and v31 1/2 the frequency set by dc0, dc1 notes: 1. the power efficiency can be improved by halting grayscale amplifiers and slowing down the step-up clock frequency only in non-display drive period. 2. the gate output level in non-lit display area drive period is determined by ptg[1:0].
R61503U specification rev.1.1, march 29, 2007, page 54 of 186 external display interface control 1 (r0ch) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 rm 0 0 dm [1] dm [0] 0 0 rim [1] rim [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rim[1:0]: sets interface format when rgb interface is selected by rm and dm bits. set rim[1:0] bits before starting display operation via rgb interface. do not change the setting while the R61503U performs display operation. table 20 rgb interface operation rim[1:0] rgb inte rface operation 2?h0 18-bit rgb interface (1 transfer/pixel) 2?h1 16-bit rgb interface (1 transfer/pixel) 2?h2 6-bit rgb interface (3 transfers/pixel) 2?h3 setting inhibited notes: 1: instruction bits are set via system interface. 2: transfer the rgb dot data one by one in synchronization with dotclk in 6-bit rgb interface operation. dm[1:0]: selects the interface for the display operation. the dm[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. however, switching between the rgb interface operation mode and the vsync interface operation mode is prohibited. table 21 display interface dm[1:0] display interface 2?h0 internal clock operations 2?h1 rgb interface 2?h2 vsync interface 2?h3 setting inhibited rm: selects the interface for ram access operation. ram access is possible only via the interface selected by the rm bit. set rm = 1 when writing display data via rgb interface. when rm = 0, it is possible to write data via system interface while performing display operation via rgb interface. table 22 ram access interface rm ram access interface 0 system interface/vsync interface 1 rgb interface
R61503U specification rev.1.1, march 29, 2007, page 55 of 186 the R61503U selects the optimum interface according to the displayed image by setting instruction as follows. in moving picture display operation via rgb or vsync interface, write data in high-speed write mode (hwm = 1) in order to access ram in high-speed with low power consumption. table 23 the state of display operation mode ram access (rm) display operation mode (dm) still pictures internal clock operation system interface (rm = 0) internal clock operation (dm1-0 = 00) moving pictures rgb interface (1) rgb interface (rm = 1) rgb interface (dm1-0 = 01) rewrite still picture area while displaying moving pictures. rgb interface (2) system interface (rm = 0) rgb interface (dm1-0 = 01) moving pictures vsync interface system interface (rm = 0) vsync interface (dm1-0 = 10) notes: 1. instructions are set only via system interface. 2. the rgb and vsync interfaces cannot be used simultaneously. 3. do not make changes to the rgb interface operation setting (rim1-0) while rgb interface is in operation. 4. see the ?external display interface? section for the sequences when switching from one mode to another. 5. use high-speed write function (hwm = 1) when writing data via rgb or vsync interface. internal clock operation the display operation is synchronized with signals generated from internal oscillator?s clock (osc) in this mode. all input via external display interface is disabled in this operation. the internal ram can be accessed only via system interface. rgb interface operation (1) the display operation is synchronized with frame synchronous signal (vsync), line synchronous signal (hsync), and dot clock signal (dotclk) in rgb interface operation. these signals must be supplied during the display operation via rgb interface. the R61503U transfers display data in units of pixels via db17-0 pins. the display data is stored in the internal ram. the combined use of high-speed ram write mode and window address function can minimize the total number of data transfer for moving picture display by transferring only the data to be written in the moving picture ram area when it is written and enables the R61503U to display a moving picture and the data in other than the moving picture ram area simultaneously. the front porch (fp), back porch (bp), and the display (nl) periods are automatically calculated inside the R61503U by counting the number of clocks of line synchronous signal (hsync) from the falling edge of the frame synchronous signal (vsync). make sure to transfer pixel data via db17-0 pins in accordance with the settings of these periods.
R61503U specification rev.1.1, march 29, 2007, page 56 of 186 rgb interface operation (2) this mode enables the R61503U to rewrite ram data via system interface while using rgb interface for display operation. to rewrite ram data via system interface, make sure that display data is not transferred via rgb interface (enable = high). to return to the rgb interface operation, change the enable setting first. then set an address in the ram address set register and r22h in the index register. vsync interface operation the internal display operation is synchronized with the frame synchronous signal (vsync) in this mode. this mode enables the R61503U to display a moving picture via system interface by writing data in the internal ram at faster than the calculated minimum speed via system interface from the falling edge of frame synchronous (vsync). in this case, there are restrictions in speed and method of writing ram data. for details, see the ?vsync interface? section. as external input, only vsync signal input is valid in this mode. other input via external display interface becomes disabled. the front porch (fp), back porch (bp), and the display (nl) periods are automatically calculated from the frame synchronous signal (vsync) inside the R61503U according to the instruction settings for these periods.
R61503U specification rev.1.1, march 29, 2007, page 57 of 186 external display interface control 2 (r0fh) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 vsp l hsp l 0 epl dpl default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dpl: sets the signal polarity of the dotclk pin. dpl = ?0? the data is input on the rising edge of dotclk dpl = ?1? the data is input on the falling edge of dotclk epl: sets the signal polarity of the enable pin. epl = ?0? the data db17-0 is written when enable = ?0?. disable data write operation when enable = ?1?. epl = ?1? the data db17-0 is written when enable = ?1?. disable data write operation when enable = ?0?. hspl: sets the signal polarity of the sync pin. hspl = ?0? low active hspl = ?1? high active vspl: sets the signal polarity of the vsync pin. vspl = ?0? low active vspl = ?1? high active
R61503U specification rev.1.1, march 29, 2007, page 58 of 186 power control power control 1/2 (r10h/r11h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 sap bt [3] bt [2] bt [1] bt [0] ape 0 ap [1] ap [0] 0 dst b slp stb default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 dc1 [2] dc1 [1] dc1 [0] 0 dc0 [2] dc0 [1] dc0 [0] 0 vc [2] vc [1] vc [0] default 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 top: r10h, bottom: r11h stb: when stb = 1, the R61503U enters the standby mode. in standby mode, the R61503U halts rc oscillation and receiving external clock signal to halt the display operation completely. in setting the standby mode, follow the standby mode setting sequence. the R61503U accepts only the following instructions in standby mode. the instruction register setting is retained in standby mode. 1. exit standby mode (stb = 0) 2. start oscillation slp: when slp = 1, the R61503U enters the sleep mode. in sleep mode, the internal display operation except rc oscillation is halted to reduce power consumption. no change to the gram data and instruction setting is accepted and the gram data and the instruction setting are maintained in sleep mode. dstb: when dstb = 1, the R61503U enters the deep standby mode. in deep standby mode, the internal logic power supply is turned off to reduce power consumption. the gram data and instruction setting are not maintained when the R61503U enters the deep standby mode, and they must be reset after exiting deep standby mode. ap[1:0]: adjusts the constant current in the operational amplifier circuit in the lcd power supply circuit. the larger constant current enhances the drivability of the lcd, but it also increases the current consumption. adjust the constant current taking the trade-off into account between the display quality and the current consumption. in no-display period, set ap1-0 = 2?h0 to halt the operational amplifier circuits and the step-up circuits to reduce current consumption. ape: liquid crystal power supply enable bit. set ape = ?1? when starting the generation of liquid crystal power supply according to the liquid crystal power supply startup sequence. after starting up the power supply circuit, set ape = ?1?. table 24 ape liquid crystal power supply circuit grayscale voltage generating circuit 1?h0 halt halt 1?h1 operate operate bt[3:0]: sets the factor used in the step-up circuits. select the optimal step-up factor for the operating voltage. to reduce power consumption, set a smaller factor.
R61503U specification rev.1.1, march 29, 2007, page 59 of 186 sap: when sap = ?0?, the internal source output circuit is halted (s1-s528 = gnd). when sap = ?1?, grayscale voltages are output from the source output circuit. set sap = ?0? when turning on the power supply such as liquid crystal power supply circuit. after starting up the power supply circuit, set sap = ?1?. vc[2:0]: sets the factor of vcilvl to generate the reference voltages vciout, vci1. dc0[2:0]: selects the operating frequency of the step-up circuit 1. the higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. adjust the frequency taking the trade-off between the display quality and the current consumption into account. dc1[2:0]: selects the operating frequency of the step-up circuit 2. the higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. adjust the frequency taking the trade-off between the display quality and the current consumption into account. table 25 step-up factor for step-up circuits 1/2 bt[3:0] ddvdh vcl vgh vgl capacitor connection pins 3?h0 -(vci1+ddvdh2) [x -5] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?h1 -(ddvdh2) [x -4] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?h2 ddvdh3 [x 6] -(vci1+ddvdh) [x -3] ddvdh, vgh, vgl, vcl c11, c13, c21, c22, 3?h3 -(vci1+ddvdh2) [x -5] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?h4 -(ddvdh2) [x -4] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?h5 vci1+ddvdh2 [x 5] -(vci1+ddvdh) [x -3] ddvdh, vgh, vgl, vcl c11, c13c21, c22 3?h6 -(ddvdh2) [x -4] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?h7 vci12 [x 2] -vci1 ddvdh2 [x 4] -(vci1+ddvdh) [x -3] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?h8 setting disabled 3?h9 vci12 [x 2] -vci1 ddvdh3 [x 6] -(vddvdh) [x -2] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?ha setting disabled 3?hb setting disabled 3?hc vci12 [x 2] -vci1 vci1+ddvdh2 [x 5] -(vddvdh) [x -2] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?hd setting disabled 3?he vci12 [x 2] -vci1 ddvdh2 [x 4] -(vddvdh) [x -2] ddvdh, vgh, vgl, vcl c11, c13, c21, c22 3?hf setting disabled notes: 1. the factors in the brackets show the step-up factors from vci1. 2.connect capacitors to the capacitor connection pins when generating ddvdh, vgh, vgl levels. 3. make sure ddvdh = max. 6.0v, vgh-vgl (amplitude) = max. 28.0v.
R61503U specification rev.1.1, march 29, 2007, page 60 of 186 table 26 constant current in operational amplifiers ap[1:0] in lcd drive power supply amplifiers in grayscale voltage amplifiers 2?h0 halt operational amplifiers and step-up circuits halt 2?h1 0.5 0.62 2?h2 0.75 0.71 2?h3 1 1 note: the values in the table represent the ratios of currents in respective settings to the current when ap[1:0] = 2?h3. table 27 operating frequencies of step-up circuits 1/2 dc0[2:0] step-up circuit 1 operating frequency (f dcdc1 ) dc1[2:0] step-up circuit 2 operating frequency (f dcdc2 ) 3?h0 fosc / 8 3?h0 fosc / 16 3?h1 fosc / 16 3?h1 fosc / 32 3?h2 fosc / 32 3?h2 fosc / 64 3?h3 fosc / 64 3?h3 fosc / 128 3?h4 fosc / 128 3?h4 fosc / 256 3?h5 setting disabled 3?h5 setting disabled 3?h6 halt the step-up circuit 1 3?h6 halt the step-up circuit 2 3?h7 setting disabled 3?h7 setting disabled note: make sure f dcdc1 f dcdc2 when setting the operating frequencie s of the step-up circuits 1/2. table 28 reference voltage setting vc[2:0] vciout (reference voltage) vci1 voltage 3?h0 0.94 x vcilvl 3?h1 0.89 x vcilvl 3?h2 setting disabled 3?h3 setting disabled 3?h4 0.76 x vcilvl 3?h5 setting disabled 3?h6 setting disabled 3?h7 1.00 x vcilvl
R61503U specification rev.1.1, march 29, 2007, page 61 of 186 power control 3/4 (r12h/r13h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 von 0 0 0 vcm r vre g1r 0 ps on pon vrh [3] vrh [2] vrh [1] vrh [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 vco mg 0 0 0 vdv [3] vdv [2] vdv [1] vdv [0] vcm sel 0 0 vcm [4] vcm [3] vcm [2] vcm [1] vcm [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 top: r12h, bottom: r13h vrh[3:0]: sets the factor (1.40 ~ 2.10) of vcilvl, the level of which is determined by instruction (vc), to generate the vreg1out voltage. pon: controls on/off of the vgl output. when setting the pon bit, follow the power supply startup sequence. pon = ?0?: stop the step-up operation to generate vgl. pon = ?1?: start the step-up operation to generate vgl. pson: starts up the internal power supply sequencer. first set pse = ?1? to enable the internal power supply sequencer and then set pson = 1 to start up the internal power supply sequencer. vreg1r: sets vreg1out reference electrical potential. table 29 vreg1r vreg1out reference electrical potential 0 vcilvl 1 the setting in the reference voltage output electric potential ( 2.0%) vcmr: selects either external resistor (vcomr) or internal electric volume (vcm) to set the electrical potential of vcomh (vcom center voltage level). table 30 vcmr vcomh electrical potential 0 vcomr (variable resistor) 1 internal electronic volume note: the internal electronic volume is set by instruction (vcm[4:0]). von: controls vcom output and its output level in combination with the following bit setting.
R61503U specification rev.1.1, march 29, 2007, page 62 of 186 table 31 von vcomg vcom output level 0 * gnd 1 0 vcomh/gnd 1 1 vcomh/vcoml vcm[4:0]: selects the internal electronic volume applied to vreg1out to set the vcomh electrical potential. set vcmr = 1 when setting the vcomh electrical potential with internal electronic volume. vcmsel: selects either the setting in the internal register (vcm[4:0]) or the setting written in the internal nv memory (r29h or r2ah) to set the vcomh level. vdv[3:0]: sets the factor applied to vreg1out to define the amplitude of vcom. table 32 vreg1out vreg1out vreg1out vrh[3:0] vreg1r = 0 vreg1r = 1 vrh[3:0] vreg1r = 0 vreg1r = 1 4?h0 halt (hi-z) halt (hi-z) 4?h8 vcilvl x 1.75 4.375v 4?h1 vcilvl x 1.40 3.5v 4?h9 vcilvl x 1.80 4.5v 4?h2 vcilvl x 1.45 3.625v 4?ha vcilvl x 1.85 4.625v 4?h3 vcilvl x 1.50 3.75v 4?hb vcilvl x 1.90 4.75v 4?h4 vcilvl x 1.55 3.875v 4?hc vcilvl x 1.95 4.875v 4?h5 vcilvl x 1.60 4.0v 4?hd vcilvl x 2.00 5.0v 4?h6 vcilvl x 1.65 4.125v 4?he vcilvl x 2.05 5.125v 4?h7 vcilvl x 1.70 4.25v 4?hf vcilvl x 2.10 5.25v note: set vc and vrh so that vreg1out becomes equal or less than 3.5 v ~ (ddvdh -5.0)v. table 33 vcmsel vcomh level setting 0 enable the setting in r13h (vcm[4:0]) 1 enable the setting in the internal nv memory (r29h or r2ah)
R61503U specification rev.1.1, march 29, 2007, page 63 of 186 table 34 vcm: internal electronic volume adjustment vcm[4:0] vcomh vcm[4:0] vcomh 5?h00 vreg1out x 0.69 5?h10 vreg1out x 0.85 5?h01 vreg1out x 0.70 5?h11 vreg1out x 0.86 5?h02 vreg1out x 0.71 5?h12 vreg1out x 0.87 5?h03 vreg1out x 0.72 5?h13 vreg1out x 0.88 5?h04 vreg1out x 0.73 5?h14 vreg1out x 0.89 5?h05 vreg1out x 0.74 5?h15 vreg1out x 0.90 5?h06 vreg1out x 0.75 5?h16 vreg1out x 0.91 5?h07 vreg1out x 0.76 5?h17 vreg1out x 0.92 5?h08 vreg1out x 0.77 5?h18 vreg1out x 0.93 5?h09 vreg1out x 0.78 5?h19 vreg1out x 0.94 5?h0a vreg1out x 0.79 5?h1a vreg1out x 0.95 5?h0b vreg1out x 0.80 5?h1b vreg1out x 0.96 5?h0c vreg1out x 0.81 5?h1c vreg1out x 0.97 5?h0d vreg1out x 0.82 5?h1d vreg1out x 0.98 5?h0e vreg1out x 0.83 5?h1e vreg1out x 0.99 5?h0f vreg1out x 0.84 5?h1f vreg1out x 1.00 notes 1. set vcomh from (ddvdh-0.5)v to 2.5v. 2. the vcm[4:0] setting is enabled when vcmr = 1. table 35 vdv: vcs (= vcom) amplitude vdv[3:0] vcs (= vcom) amplitude 4?h00 vreg1out x 0.70 4?h01 vreg1out x 0.72 4?h02 vreg1out x 0.74 4?h03 vreg1out x 0.76 4?h04 vreg1out x 0.78 4?h05 vreg1out x 0.80 4?h06 vreg1out x 0.82 4?h07 vreg1out x 0.84 4?h08 vreg1out x 0.86 4?h09 vreg1out x 0.88 4?h0a vreg1out x 0.90 4?h0b vreg1out x 0.92 4?h0c vreg1out x 0.94 4?h0d vreg1out x 0.96 4?h0e vreg1out x 0.98 4?h0f vreg1out x 1.00 note: set the vcom amplitude from 2.5v to (ddvdh-0.5)v.
R61503U specification rev.1.1, march 29, 2007, page 64 of 186 vcomg: when vcomg = 1, the vcoml voltage can be set in the negative range (1.0 ~ vci+0.5v (max.)). when vcomg = 0, the amplifiers for the negative voltage are halted to reduce power consumption. when vcomg = 0, the vdv[3:0] setting is disabled. in this case the vcom alternating amplitude is determined by the vcm[4:0] setting, which determines the vcomh level. pon must be set to 1 the setting vcomg = 1 is enabled. power sequence control 5 (r14h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 dc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dc5: changes the cycle of base clock for the step-up operation. when setting dc5 = 1, the step-up clock is synchronized with the 1h period, i.e. the step-up clock is reset every 1h period. by changing the setting of dc5 bit, the step-up clock cycles dc0 and dc1 are also changed. table 36 dc5 base clock f bc 0 f osc 1 f osc /2, synchronized with the 1h period table 37 operating frequencies of step-up circuits 1/2 dc0[2:0] step-up circuit 1 operating frequency (f dcdc1 ) dc1[2:0] step-up circuit 2 operating frequency (f dcdc2 ) 3?h0 f bc / 8 3?h0 f bc / 16 3?h1 f bc / 16 3?h1 f bc / 32 3?h2 f bc / 32 3?h2 f bc / 64 3?h3 f bc / 64 3?h3 f bc / 128 3?h4 f bc / 128 3?h4 f bc / 256 3?h5 setting disabled 3?h5 setting disabled 3?h6 halt the step-up circuit 1 3?h6 halt the step-up circuit 2 3?h7 setting disabled 3?h7 setting disabled
R61503U specification rev.1.1, march 29, 2007, page 65 of 186 f osc 1h counter 00h ... 03h 04h ... 07h 08h ... 0bh 0ch ... 0fh 10h 11h 12h 13h rtn3-0 = 4h: 1h counter = 00h ~ 13h f bc f dcdc1 8 clocks 12 clocks f bc: stop dc5 = 1: f bc: = f osc /2 dc02-00 = 3h: f dcdc1 = f bc /8 figure 15 power control 6 (r18h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pse default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pse: power supply startup enable bit. the power supply startup operation is started by setting pson = 1 when pse = 1. when the power supply startup operation is completed, the pse bit is set to ?0?.
R61503U specification rev.1.1, march 29, 2007, page 66 of 186 ram access instruction ram address set horizontal address (r20h), ram address set vertical address (r21h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 ad [7] ad [6] ad [5] ad [4] ad [3] ad [2] ad [1] ad [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 0 ad [16] ad [15] ad [14] ad [13] ad [12] ad [11] ad [10] ad [9] ad [8] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 top: r20h, bottom: r21h ad[16:0]: a gram address set initially in the ac (address counter). the address in the ac is automatically updated according to the am, i/d[1:0] settings as the R61503U writes data to the internal gram so that data can be written consecutively without resetting the address in the ac. the address is not automatically updated when reading data from the internal gram. note 1: in rgb interface operation (rm = ?1?), the address ad16-0 is set in the address counter every frame on the falling edge of vsync. note 2: in internal clock operation and vsync interface operation (rm = ?0?), the address ad16-0 is set when executing the instruction. table 38 gram address range ad[16:0] gram setting 17?h00000 ~ 17?h 000af bitmap data for g1 ?00100? ~ ?001af? bitmap data for g2 ?00200? ~ ?002af? bitmap data for g3 ?00300? ~ ?003af? bitmap data for g4 : : ?0d800? ~ ?0d8af? bitmap data for g217 ?0d900? ~ ?0d9af? bitmap data for g218 ?0da00? ~ ?0daaf? bitmap data for g219 ?0db00? ~ ?0dbaf? bitmap data for g220
R61503U specification rev.1.1, march 29, 2007, page 67 of 186 write/read ram data write data to gram (r22h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 ram write data wd[17:0] is transferred via diffe rent data bus in different interface operation. wd[17:0]: the R61503U develops data into 18 bits internally in write operation. the format to develop data into 18 bits is different in different interface operation. the gram data represents the grayscale level. the R61503U automatically updates the address according to am and i/d[1:0] settings as it writes data in the gram. in deep standby mode, gram access is disenabled. in 8-/16-bit interface operation, the msbs of r and b dot are written as the lsbs of respective dot to expand data into 18 bits. in this case, 65,536 colors are available. note: when writing data in gram via system interface while using the rgb interface, make sure that write operations via two interfaces do not conflict with each other.
R61503U specification rev.1.1, march 29, 2007, page 68 of 186 table 39 gram data and lcd output level (rev = ?0?) selected grayscale selected grayscale gram data (rgb) negative positive gram data (rgb) negative positive 000000 v0 v31 100000 v16 v15 000001 (v0+v1)/2 (v30+v31)/2 100001 (v16+v17)/2 (v14+v15)/2 000010 v1 v30 100010 v17 v14 000011 (v1+v2)/2 (v29+v30)/2 100011 (v17+v18)/2 (v13+v14)/2 000100 v2 v29 100100 v18 v13 000101 (v2+v3)/2 (v28+v29)/2 100101 (v18+v19)/2 (v12+v13)/2 000110 v3 v28 100110 v19 v12 000111 (v3+v4)/2 (v27+v28)/2 100111 (v19+v20)/2 (v11+v12)/2 001000 v4 v27 101000 v20 v11 001001 (v4+v5)/2 (v26+v27)/2 101001 (v20+v21)/2 (v10+v11)/2 001010 v5 v26 101010 v21 v10 001011 (v5+v6)/2 (v25+v26)/2 101011 (v21+v22)/2 (v9+v10)/2 001100 v6 v25 101100 v22 v9 001101 (v6+v7)/2 (v24+v25)/2 101101 (v22+v23)/2 (v8+v9)/2 001110 v7 v24 101110 v23 v8 001111 (v7+v8)/2 (v23+v24)/2 101111 (v23+v24)/2 (v7+v8)/2 010000 v8 v23 110000 v24 v7 010001 (v8+v9)/2 (v22+v23)/2 110001 (v24+v25)/2 (v6+v7)/2 010010 v9 v22 110010 v25 v6 010011 (v9+v10)/2 (v21+v22)/2 110011 (v25+v26)/2 (v5+v6)/2 010100 v10 v21 110100 v26 v5 010101 (v10+v11)/2 (v20+v21)/2 110101 (v26+v27)/2 (v4+v5)/2 010110 v11 v20 110110 v27 v4 010111 (v11+v12)/2 (v19+v20)/2 110111 (v27+v28)/2 (v3+v4)/2 011000 v12 v19 111000 v28 v3 011001 (v12+v13)/2 (v18+v19)/2 111001 (v28+v29)/2 (v2+v3)/2 011010 v13 v18 111010 v29 v2 011011 (v13+v14)/2 (v17+v18)/2 111011 (v29+v30)/2 (v1+v2)/2 011100 v14 v17 111100 v30 v1 011101 (v14+v15)/2 (v16+v17)/2 111101 (v30+v31)/2 (v0+v1)/2 011110 v15 v16 111110 (v30+2xv31)/3 (2xv0+v1)/3 011111 (v15+v16)/2 (v15+v16)/2 111111 v31 v0
R61503U specification rev.1.1, march 29, 2007, page 69 of 186 ram access via rgb interface and system interface the R61503U writes all data in gram in rgb interface operation in order to rewrite the data only within the moving picture area and transfer only the data to be written over the moving picture area. the power consumption required for moving picture display can be reduced and ram data update can be done in short period by specifying window address area and enabling high-speed write function. the R61503U also allows writing the display data in other than the moving picture area in gram via system interface while not updating the moving picture frame. the R61503U allows ram access via system interface in rgb interface operation. in rgb interface operation, the data is written to the internal ram in synchronization with dotclk while enable is ?low?. when writing data to the ram via system interface, set enable ?high? to stop writing data via rgb interface. when switching to ram access via rgb interface from ram access via system interface, make sure to wait for read/write bus cycle time. if there is a conflict between ram accesses via two interfaces, there is no guarantee that the data is written in the ram. index r2 2 ram address set rewrite data outside the moving picture ram area rm= 1 index r2 2 rewrite moving picture area 2004/01/01 00:00 2 0 0 4 / 0 1 / 0 1 0 0 : 0 0 frame rewrite rewrite still picture ram address set frame rewrite rewrite moving picture area note 1) in rgb interface operation, ram address (ad16-0) is set in the address counter on the falling edge of vsync. note 2) set a ram address (ad16-0) and the index to r22h before starting ram access via rgb interface. note 3) use high-speed write function (hwm = "1") when writing data via rgb interface. note 2) moving picture area vsync enable dotclk db17-0 system interface rm=0 figure 16
R61503U specification rev.1.1, march 29, 2007, page 70 of 186 read data from gram (r22h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r 1 ram read data rd[17:0] is transferred via different data bus in different interface operation. rd[17:0]: 18-bit data read from the gram. ram read data rd[17:0] is transferred via different data bus in different interface operation. when the R61503U reads data from the gram to the microcomputer, the first word, which is read immediately after the ram address set instruction is executed, is taken in the internal read-data latch and invalid data is sent to the data bus. valid data is sent to the data bus when the R61503U reads out the second and subsequent words. when either 8-bit or 16-bit interface is selected, the lsbs of r and b dot data are not read out. note: this register is not available in rgb interface operation. set address n (ad16-0) set address m (ad16-0) first word first word second word second word set i/d, am, hsa, hea, vsa, and vea bits dummy read (invalid data to db17-0) transfer gram data to read data latch read (data of address n) from read data latch to db17-0 read out data to the microcomputer dummy read (invalid data to db17-0) transfer gram data to read data latch read (data of address m) from read data latch to db17-0 figure 17 gram read sequence
R61503U specification rev.1.1, march 29, 2007, page 71 of 186 nv memory read data 1/2/3 (r28h/r29h/r2ah) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r28 w 1 0 0 0 0 0 0 0 0 0 0 0 0 uid [3] uid [2] uid [1] uid [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r29 w 1 0 0 0 0 0 0 0 0 evc me0 0 0 evcm 0[4] evcm 0[3] evcm 0[2] evcm 0[1] evcm 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r2a w 1 0 0 0 0 0 0 0 0 evc me1 0 0 evcm 1[4] evcm 1[3] evcm 1[2] evcm 1[1] evcm 1[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uid[3:0]: data in address 1, which is read from the internal nv memory and used as the user identification code. see ?nv memory control? for details. evcme0, evcm1: select either evcm0[4:0] or evcm1[4:0] in the internal nv memory to set the vcomh level when setting vcomh by internal electronic volume. when vcmsel = 1, the setting written in the internal nv memory, i.e. either evcm0[4:0] or evcm1[4:0], is used instead of vcm[4:0], i.e. internal register setting. table 40 evcme1 evcme0 vcomh setting 0 0 6?h0 0 1 evcm0[4:0] (data written in address 2) 1 0 setting disabled 1 1 evcm1[4:0] (data written in address 3) evcm0[4:0]: data in address 2 in the nv memory to adjust the vcomh voltage using internal electronic volume. evcm1[4:0]: data in address 3 in the nv memory to adjust the vcomh voltage using internal electronic volume.
R61503U specification rev.1.1, march 29, 2007, page 72 of 186 control instruction control (1) ~ (9) (r30h ~ r3ah) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r30 w 1 0 0 0 0 0 pkp 1[2] pkp 1[1] pkp 1[0] 0 0 0 0 0 pkp 0[2] pkp 0[1] pkp 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r31 w 1 0 0 0 0 0 pkp 3[2] pkp 3[1] pkp 3[0] 0 0 0 0 0 pkp 2[2] pkp 2[1] pkp 2[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r32 w 1 0 0 0 0 0 pkp 5[2] pkp 5[1] pkp 5[0] 0 0 0 0 0 pkp 4[2] pkp 4[1] pkp 4[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r33 w 1 0 0 0 0 0 prp 1[2] prp 1[1] prp 1[0] 0 0 0 0 0 prp 0[2] prp 0[1] prp 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r34 w 1 0 0 0 0 0 pkn 1[2] pkn 1[1] pkn 1[0] 0 0 0 0 0 pkn 0[2] pkn 0[1] pkn 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r35 w 1 0 0 0 0 0 pkn 3[2] pkn 3[1] pkn 3[0] 0 0 0 0 0 pkn 2[2] pkn 2[1] pkn 2[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r36 w 1 0 0 0 0 0 pkn 5[2] pkn 5[1] pkn 5[0] 0 0 0 0 0 pkn 4[2] pkn 4[1] pkn 4[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r37 w 1 0 0 0 0 0 prn 1[2] prn 1[1] prn 1[0] 0 0 0 0 0 prn 0[2] prn 0[1] prn 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r38 w 1 0 0 0 vrp 1[4] vrp 1[3] vrp 1[2] vrp 1[1] vrp 1[0] 0 0 0 vrp 0[4] vrp 0[3] vrp 0[2] vrp 0[1] vrp 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r39 w 1 0 0 0 vrn 1[4] vrn 1[3] vrn 1[2] vrn 1[1] vrn 1[0] 0 0 0 vrn 0[4] vrn 0[3] vrn 0[2] vrn 0[1] vrn 0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pkp5-0[2:0] fine adjustment register for positive polarity prp1-0[2:0] gradient adjustment register for positive polarity pkn5-0[2:0] fine adjustment register for negative polarity prn1-0[2:0] gradient adjustment register for negative polarity vrp1-0[4:0] amplitude adjustment register for positive polarity vrn1-0[4:0] amplitude adjustment register for negative polarity see ? correction function? for details.
R61503U specification rev.1.1, march 29, 2007, page 73 of 186 window address control instruction window horizontal ram start address (r50h), window horizontal ram end address (r51h) window vertical ram start address (r52h), window vertical ram end address (r52h), r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r50 w 1 0 0 0 0 0 0 0 0 hsa [7] hsa [6] hsa [5] hsa [4] hsa [3] hsa [2] hsa [1] hsa [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r51 w 1 0 0 0 0 0 0 0 0 hea [7] hea [6] hea [5] hea [4] hea [3] hea [2] hea [1] hea [0] default 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 r52 w 1 0 0 0 0 0 0 0 vsa [8] vsa [7] vsa [6] vsa [5] vsa [4] vsa [3] vsa [2] vsa [1] vsa [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r53 w 1 0 0 0 0 0 0 0 vea [8] vea [7] vea [6] vea [5] vea [4] vea [3] vea [2] vea [1] vea [0] default 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 hsa[7:0]/hea[7:0]: hsa[7:0] and hea[7:0] are the start and end addresses of the window address area in horizontal direction, respectively. hsa[7:0] and hea[7:0] specify the horizontal range to write data. set hsa[7:0] and hea[7:0] before starting ram write operation. in setting, make sure that ?00?h hsa[7:0] < hea[7:0] ?af?h. vsa[8:0]/vea[8:0]: vsa[8:0] and vea[8:0] are the start and end addresses of the window address area in vertical direction, respectively. vsa[8:0] and vea[8:0] specify the vertical range to write data. set vsa[8:0] and vea[8:0] before starting ram write operation. in setting, make sure that ?00?h vsa[8:0] < vea[8:0] ?db?h. 00 000 0dbaf window address gram address space hea hsa vsa vea note 1) make window address area within the gram address area. window address setting area ?00?h ? hsa7-0 ? hea7-0 ? ?af"h "000?h ? vsa8-0 ? vea8-0 ? ?0db"h figure 18 gram address map and window address area
R61503U specification rev.1.1, march 29, 2007, page 74 of 186 base image display control instruction driver output control (r70h), base image display control (r71h), vertical scroll control (r7ah), r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r70 w 1 gs 0 0 nl [4] nl [3] nl [2] nl [1] nl [0] 0 0 0 scn [4] scn [3] scn [2] scn [1] scn [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r71 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vle rev default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r7a w 1 0 0 0 0 0 0 0 0 vl [7] vl [6] vl [5] vl [4] vl [3] vl [2] vl [1] vl [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 scn[4:0]: specifies the gate line where the gate driver starts scan. table 41 scan start position sm=0 sm=1 scn [4:0] gs=0 gs=1 gs=0 gs=1 4'h00 g1 g220 g1 g220 4'h01 g9 g212 g17 g204 4'h02 g17 g204 g33 g188 4'h03 g25 g196 g49 g172 4'h04 g33 g188 g65 g156 4'h05 g41 g180 g81 g140 4'h06 g49 g172 g97 g124 4'h07 g57 g164 g113 g108 4'h08 g65 g156 g129 g92 4'h09 g73 g148 g145 g76 4'h0a g81 g140 g161 g60 4'h0b g89 g132 g177 g44 4'h0c g97 g124 g193 g28 4'h0d g105 g116 g209 g12 4'h0e g113 g108 g9 g216 4'h0f g121 g100 g25 g200 4'h10 g129 g92 g41 g184 4'h11 g137 g84 g57 g168 4'h12 g145 g76 g73 g152 4'h13 g153 g68 g89 g136 4'h14 g161 g60 g105 g120 4'h15 g169 g52 g121 g104 4'h16 g177 g44 g137 g88 4'h17 g185 g36 g153 g72 4'h18 g193 g28 g169 g56 4'h19 g201 g20 g185 g40 4'h1a g209 g12 g201 g24 4'h1b g217 g4 g217 g8 4'h1c-4'h1f setting disabled setting disabled setting disabled setting disabled
R61503U specification rev.1.1, march 29, 2007, page 75 of 186 nl[4:0]: sets the number of lines to drive the lcd at an interval of 8 lines. the gram address mapping is not affected by the number of lines set by nl[4:0]. the number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. table 42 nl [4:0] lcd drive line nl [4:0] lcd drive line 6'h00 0 line 6'h10 136 lines 6'h01 16 lines 6'h11 144 lines 6'h02 24 lines 6'h12 152 lines 6'h03 32 lines 6'h13 160 lines 6'h04 40 lines 6'h14 168 lines 6'h05 48 lines 6'h15 176 lines 6'h06 56 lines 6'h16 184 lines 6'h07 64 lines 6'h17 192 lines 6'h08 72 lines 6'h18 200 lines 6'h09 80 lines 6'h19 208 lines 6'h0a 88 lines 6'h1a 216 lines 6'h0b 96 lines 6'h1b 220 lines 6'h0c 104 lines 6'h0d 112 lines 6'h0e 120 lines 6'h0f 128 lines gs: sets the direction of scan by the gate driver in the range determined by scn[4:0] and nl[4:0]. the scan direction determined by gs = 0 can be reversed by setting gs = 1. when gs = 0, the scan direction is from g1 to g220. when gs = 1, the scan direction is from g220 to g1 rev: enables the grayscale inversion of the image by setting rev = 1. this enables the R61503U to display the same image from the same set of data whether the liquid crystal panel is normally black or white. the source output level during the front, back porch periods and blank periods is determined by register setting (pts). table 43 gram data-grayscale level inversion source output level in display area rev gram data positive polarity negative polarity 18?h00000 v31 v0 : : : 0 18?hfffff v0 v31 18?h00000 v0 v31 : : : 1 18?hfffff v31 v0
R61503U specification rev.1.1, march 29, 2007, page 76 of 186 vle: vertical scroll display enable bit. when vle = 1, the R61503U starts displaying the base image from the line (of the physical display) determined by vl[7:0] bits. vl[7:0] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display. note that the partial image display position is not affected by the base image scrolling. the vertical scrolling is not available in external display interface operation. in this case, make sure to set vle = ?0?. table 44 vle base image 0 fixed 1 enable scrolling vl[7:0]: sets the amount of scrolling of the base image. the base image is scrolled in vertical direction and displayed from the line which is determined by vl[7:0]. make sure bsa(0) +vl[7:0] bea(220).
R61503U specification rev.1.1, march 29, 2007, page 77 of 186 partial control instruction partial image 1 display position (r80h) partial image 1 ram start address (r81h), partial image 1 ram end address (r82h) partial image 2 display position (r83h) partial image 2 ram address (r84h), partial image 2 ram end address (r85h), r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r80 w 1 0 0 0 0 0 0 0 0 ptd p0[7] ptd p0[6] ptd p0[5] ptd p0[4] ptd p0[3] ptd p0[2] ptd p0[1] ptd p0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r81 w 0 0 0 0 0 0 0 0 pts a0[7] pts a0[6] pts a0[5] pts a0[4] pts a0[3] pts a0[2] pts a0[1] pts a0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r82 w 0 0 0 0 0 0 0 0 pte a0[7] pte a0[6] pte a0[5] pte a0[4] pte a0[3] pte a0[2] pte a0[1] pte a0[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r83 w 1 0 0 0 0 0 0 0 0 ptd p1[7] ptd p1[6] ptd p1[5] ptd p1[4] ptd p1[3] ptd p1[2] ptd p1[1] ptd p1[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r84 w 1 0 0 0 0 0 0 0 0 pts a1[7] pts a1[6] pts a1[5] pts a1[4] pts a1[3] pts a1[2] pts a1[1] pts a1[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r85 w 1 0 0 0 0 0 0 0 0 pte a1[7] pte a1[6] pte a1[5] pte a1[4] pte a1[3] pte a1[2] pte a1[1] pte a1[0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ptdp0[7:0]: sets the display position of partial image 1. ptdp1[7:0]: sets the display position of partial image 2. the display areas of the partial images 1 and 2 must not overlap each another. in setting, make sure partial image 1 display area < partial image 2 display area, and coordinates of partial image 1 display area: (ptdp0, ptdp0+(ptea0 ? ptsa0)) coordinates of partial image 2 display area: (ptdp1, ptdp1+(ptea1 ? ptsa1)) if ptdp0 is set to ?8?h00?, the partial image 1 is displayed from the 1st line of the panel on the base image. ptsa0[7:0] ptea0[7:0]: sets the start line address and the end line address of the ram area storing the data of partial image 1. make sure ptsa0[7:0] ptea0[7:0]. ptsa1[7:0] ptea1[7:0]: sets the start line address and the end line address of the ram area storing the data of partial image 2. make sure ptsa1[7:0] ptea1[7:0].
R61503U specification rev.1.1, march 29, 2007, page 78 of 186 panel interface control instruction panel interface control 1 (r90h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 divi [1] divi [0] 0 0 0 0 rtni [3] rtni [2] rtni [1] rtni [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtni[3:0]: sets 1h (line) period. this setting is enabled while the R61503U?s display operation is synchronized with internal clock signal. divi[1:0]: sets the division ratio of internal clock frequency. the R61503U?s internal operation is synchronized with the frequency-divided internal clock, the frequency of which is divided by the division ratio set by divi[1:0]. when changing the divi[1:0] setting, the width of the reference clock for liquid crystal panel control signals is changed. the frame frequency can be adjusted by register setting (rtni and divi bits). when changing the number of lines to drive the liquid crystal panel, the frame frequency must be adjusted. see ?frame-frequency adjustment function? for details. divi[1:0] is disenabled in rgb interface operation. frame frequency calculation fosc frame frequency = clocks per line x division ratio x (line + bp + fp) [hz] fosc : rc oscillation frequency line: number of lines to drive the lcd (nl bits) division ratio: divi clocks per line: rtni table 45 clocks in 1h period (internal clock operation: 1 clock = 1 osc) rtni[3:0] clocks per line rtni[3:0] clocks per line 4?h0 16 clocks 4?h8 24 clocks 4?h1 17 clocks 4?h9 25 clocks 4?h2 18 clocks 4?ha 26 clocks 4?h3 19 clocks 4?hb 27 clocks 4?h4 20 clocks 4?hc 28 clocks 4?h5 21 clocks 4?hd 29 clocks 4?h6 22 clocks 4?he 30 clocks 4?h7 23 clocks 4?hf 31 clocks
R61503U specification rev.1.1, march 29, 2007, page 79 of 186 table 46 division ratio of the internal operation clock divi[1:0] division ratio internal operation clock frequency 2?h0 1/1 fosc / 1 2?h1 1/2 fosc / 2 2?h2 1/4 fosc / 4 2?h3 1/8 fosc / 8 note: fosc: rc oscillation frequency panel interface control 2 (r91h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 noi [2] noi [1] noi [0] 0 0 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 noi[2:0]: sets the gate output non-overlap period when the R61503U?s display operation is synchronized with internal clock signal. table 47 noi[2:0] gate non-overlap period 3?h0 0 clocks 3?h1 1 clock 3?h2 2 clocks 3?h3 3 clocks 3?h4 4 clocks 3?h5 5 clocks 3?h6 6 clocks 3?h7 7 clocks note: the gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (divi), from the reference point.
R61503U specification rev.1.1, march 29, 2007, page 80 of 186 panel interface control 3 (r92h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 sdti [2] sdti [1] sdti [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdti[2:0]: sets the source output position when the R61503U?s display operation is synchronized with internal clock signal. table 48 sdti[2:0] source output position 3?h0 0 clock 3?h1 1 clock 3?h2 2 clocks 3?h3 3 clocks 3?h4 4 clocks 3?h5 5 clocks 3?h6 6 clocks 3?h7 7 clocks note: the source output position is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (divi), from the reference point.
R61503U specification rev.1.1, march 29, 2007, page 81 of 186 panel interface control 4 (r93h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 dive [1] dive [0] 0 0 rtne [5] rtne [4] rtne [3] rtne [2] rtne [1] rtne [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtne[5:0]: sets rtne in combination with dive so that the number of dotclk calculated from the following formula becomes the number of dotclk included in 1h (line) period, when the R61503U?s display operation is synchronized with rgb interface signals. dive (division ratio) x rtne (dotclks) dotclks in 1h period. dive[1:0]: sets the division ratio of dotclk. the R61503U?s internal operation is synchronized with the frequency-divided dotclk, the frequency of which is divided by the division ratio set by dive[1:0]. this setting is enabled while the R61503U?s display operation is synchronized with rgb interface signals. table 49 dotclks in 1h period (rgb interface operation) rtne[5:0] clocks per line period (1h) rtne[5:0] clocks per line period (1h) rtne[5:0] clocks per line period (1h) rtne[5:0] clocks per line period (1h) 6?h00 setting inhibited 6?h10 16 clocks 6?h20 32 clocks 6?h30 48 clocks 6?h01 setting inhibited 6?h11 17 clocks 6?h21 33 clocks 6?h31 49 clocks 6?h02 setting inhibited 6?h12 18 clocks 6?h22 34 clocks 6?h32 50 clocks 6?h03 setting inhibited 6?h13 19 clocks 6?h23 35 clocks 6?h33 51 clocks 6?h04 setting inhibited 6?h14 20 clocks 6?h24 36 clocks 6?h34 52 clocks 6?h05 setting inhibited 6?h15 21 clocks 6?h25 37 clocks 6?h35 53 clocks 6?h06 setting inhibited 6?h16 22 clocks 6?h26 38 clocks 6?h36 54 clocks 6?h07 setting inhibited 6?h17 23 clocks 6?h27 39 clocks 6?h37 55 clocks 6?h08 setting inhibited 6?h18 24 clocks 6?h28 40 clocks 6?h38 56 clocks 6?h09 setting inhibited 6?h19 25 clocks 6?h29 41 clocks 6?h39 57 clocks 6?h0a setting inhibited 6?h1a 26 clocks 6?h2a 42 clocks 6?h3a 58 clocks 6?h0b setting inhibited 6?h1b 27 clocks 6?h2b 43 clocks 6?h3b 59 clocks 6?h0c setting inhibited 6?h1c 28 clocks 6?h2c 44 clocks 6?h3c 60 clocks 6?h0d setting inhibited 6?h1d 29 clocks 6?h2d 45 clocks 6?h3d 61 clocks 6?h0e setting inhibited 6?h1e 30 clocks 6?h2e 46 clocks 6?h3e 62 clocks 6?h0f setting inhibited 6?h1f 31 clocks 6?h2f 47 clocks 6?h3f 63 clocks
R61503U specification rev.1.1, march 29, 2007, page 82 of 186 table 50 division ratio of dotclk (rgb interface operation) internal operation clock unit in rgb interface operation dive[1:0] division ratio 18-bit rgb interface dotclk = 5mhz 6-bit x3 transfers rgb interface dotclk = 15mhz 2?h0 setting inhibited setting inhibited - setting inhibited - 2?h1 1/4 4 dotclks 0.8 s 12 dotclks 0.8 s 2?h2 1/8 8 dotclks 1.6 s 24 dotclks 1.6 s 2?h3 1/16 16 dotclks 3.2 s 48 dotclks 3.2 s panel interface control 5 (r94h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 noe [3 noe [2] noe [1] noe [0] 0 0 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 noe[3:0]: sets the gate output non-overlap period when the R61503U?s display operation is synchronized with rgb interface signals. table 51 noe[3:0] gate non-overlap period noe[3:0] gate non-overlap period 4?h0 0 clocks 4?h8 8 clocks 4?h1 1 clock 4?h9 9 clock 4?h2 2 clocks 4?ha 10 clocks 4?h3 3 clocks 4?hb 11 clocks 4?h4 4 clocks 4?hc 12 clocks 4?h5 5 clocks 4?hd 13 clocks 4?h6 6 clocks 4?he 14 clocks 4?h7 7 clocks 4?hf 15 clocks note: 1 clock = (number of data transfer/pixel) x dive (division ratio) [dotclk]
R61503U specification rev.1.1, march 29, 2007, page 83 of 186 panel interface control 6 (r95h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 sdte [2] sdte [1] sdte [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdte[2:0]: sets the source output position and vcom alternating position. this setting is enabled while the R61503U?s display operation is synchronized with rgb interface signals. table 52 sdte[2:0] source output position vcom alternating position 3?h0 0 clock 3?h1 1 clock 3?h2 2 clocks 3?h3 3 clocks 3?h4 4 clocks 3?h5 5 clocks 3?h6 6 clocks 3?h7 7 clocks note: 1 clock = (number of data transfer/pixel) x dive (division ratio) [dotclk]
R61503U specification rev.1.1, march 29, 2007, page 84 of 186 nv memory control nv memory access control 1 (ra0h), nv memory access control 2 (ra1h) calibration control (ra4h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 ra0 w/r 1 0 0 0 0 0 0 0 0 te 0 eop [1] eop [0] 0 0 ead [1] ead [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ra1 w/r 0 0 0 0 0 0 0 0 ed [7] ed [6] ed [5] ed [4] ed [3] ed [2] ed [1] ed [0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ra4 w/r 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 calb default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 te: enable internal nv memory control bit (eop). follow the nv memory control sequence when setting te. when resetting register (loading eop = 2?h2) and executing a calibration, te is set automatically according to the internal automatic sequence and it does not have to be set. eop[1:0]: internal nv memory control bit. follow the nv memory control sequence when setting eop[1:0]. table 53 eop[1:0] nv memory control 2?h0 halt 2?h1 write 2?h2 reset register (load) ead[1:0]: internal nv memory address. set ead[1:0] = 00 ~ 10 when writing to the internal nv memory. the ead[1:0] setting determines to which register (r28h, r29h, r2ah) the data ed[7:0] is written. ed[7:0]: the data written in the internal nv memory. table 54 ead[1:0] ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 2?h0 0 0 0 0 uid[3] uid[2] uid[1] uid[0] 2?h1 evcme0* 0 0 evcm0[4] evcm0[3] evcm0[2] evcm0[1] evcm0[0] 2?h2 evcme1* 0 0 evcm1[4] evcm1[3] evcm1[2] evcm1[1] evcm1[0] note*: make sure to write ?1? to evcme0, evcme1.
R61503U specification rev.1.1, march 29, 2007, page 85 of 186 calb: when calb = 1, the R61503U executes a calibration to the internal operation. set calb = 1 after power-on reset. the calb setting is automatically returned to ?0?.
R61503U specification rev.1.1, march 29, 2007, page 86 of 186 instruction list main category sub category upper code lower code upper index index command ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 index * * * * * * * * id7 id6 id5 id4 id3 id2 id1 id0 sr status read l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 start oscillation * * * * * * * * * * * * * * * 1 00h device code read 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 01h driver output control 1 0 0 0 0 0 sm 0 ss 0 0 0 0 0 0 0 0 02h liquid crystal drive waveform 0 0 0 0 0 1 bc0 eor 0 0 0 0 0 0 0 0 03h entry mode tri dfm1 dfm0 bgr 0 dack e hwm 0 0 id1 id0 am 0 0 0 04h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 05h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 06h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 07h display control 1 0 0 ptde1 ptde0 0 0 basee 0 0 0 gon dte cl 0 d1 d0 08h display control 2 0 0 0 0 fp3 fp2 fp1 fp0 0 0 0 0 bp3 bp2 bp1 bp0 09h display control 3 0 0 0 0 0 pts2 pts1 pts0 0 0 ptg1 ptg0 isc3 isc2 isc1 isc0 0a-0bh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ch external display interface 1 0 0 0 0 0 0 0 rm 0 0 dm1 dm0 0 0 rim1 rim0 0dh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0eh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* display control 1 0fh external display interface 2 0 0 0 0 0 0 0 0 0 0 0 vspl hspl 0 dpl epl 10h power control 1 0 0 0 sap bt3 bt2 bt1 bt0 ape 0 ap1 ap0 0 dstb slp stb 11h power control 2 0 0 0 0 0 dc12 dc11 dc10 0 dc02 dc01 dc01 0 vc2 vc1 vc0 12h power control 3 0 0 0 von 0 0 0 vcmr vreg 1r 0 pson pon vrh3 vrh2 vrh1 vrh0 13h power control 4 vcom g 0 0 0 vdv3 vdv2 vdv1 vdv0 vcm sel 0 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 14h power control 5 dc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15h- 17h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18h power control 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pse 1* power control 19h-1fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20h ram address set (horizontal direction) 0 0 0 0 0 0 0 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 21h ram address set (vertical direction) 0 0 0 0 0 0 0 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 22h ram data write/ read ram write data (wd17-0) / read data (rd17-0) bits are transferred via different data bus lines according to the selected interf ace?s format. 23h- 27h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28h nv memory read data 1 0 0 0 0 0 0 0 0 0 0 0 0 uid3 uid2 uid1 uid0 29h nv memory read data 2 0 0 0 0 0 0 0 0 evcm e0 0 0 evcm 04 evcm 03 evcm 02 evcm 01 evcm 00 2ah nv memory read data 3 0 0 0 0 0 0 0 0 evcm e1 0 0 evcm 14 evcm 13 evcm 12 evcm 11 evcm 10 2* ram access 2bh- 2fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30h gamma control 1 0 0 0 0 0 pkp 12 pkp 11 pkp 10 0 0 0 0 0 pkp 02 pkp 01 pkp 00 31h gamma control 2 0 0 0 0 0 pkp 32 pkp 31 pkp 30 0 0 0 0 0 pkp 22 pkp 21 pkp 20 32h gamma control 3 0 0 0 0 0 pkp 52 pkp 51 pkp 50 0 0 0 0 0 pkp 42 pkp 41 pkp 40 33h gamma control 4 0 0 0 0 0 prp 12 prp 11 prp 10 0 0 0 0 0 prp 02 prp 01 prp 00 34h gamma control 5 0 0 0 0 0 pkn 12 pkn 11 pkn 10 0 0 0 0 0 pkn 02 pkn 01 pkn 00 35h gamma control 6 0 0 0 0 0 pkn 32 pkn 31 pkn 30 0 0 0 0 0 pkn 22 pkn 21 pkn 20 36h gamma control 7 0 0 0 0 0 pkn 52 pkn 51 pkn 50 0 0 0 0 0 pkn 42 pkn 41 pkn 40 37h gamma control 8 0 0 0 0 0 prn 12 prn 11 prn 10 0 0 0 0 0 prn 02 prn 01 prn 00 38h gamma control 9 0 0 0 vrp 14 vrp 13 vrp 12 vrp 11 vrp 10 0 0 0 vrp 04 vrp 03 vrp 02 vpr 01 vrp 00 39h gamma control 10 0 0 0 vrn 14 vrn 13 vrn 12 vrn 11 vrn 10 0 0 0 vrn 04 vrn 03 vrn 02 vrn 01 vrn 00 3* gamma control 3ah gamma control 11 0 0 0 vajn 14 vajn 13 vajn 12 vajn 11 vajn 10 0 0 0 vajp 04 vajp 03 vajp 02 vajp 01 vajp 00
R61503U specification rev.1.1, march 29, 2007, page 87 of 186 main category sub category upper code lower code upper index index command ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 3bh-3fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4* 40h- 4fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50h horizontal ram address start position 0 0 0 0 0 0 0 0 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 51h horizontal ram address end position 0 0 0 0 0 0 0 0 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 52h vertical ram address start position 0 0 0 0 0 0 0 vsa8 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 53h vertical ram address end position 0 0 0 0 0 0 0 vea8 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 5* window address control 54h- 5fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6* 60h- 6fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70h driver output control 2 gs 0 0 nl4 nl3 nl2 nl1 nl0 0 0 0 scn4 scn3 scn2 scn1 scn0 71h base image display control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vle rev 72h- 79h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7ah vertical scroll control 0 0 0 0 0 0 0 0 vl7 vl6 vl5 vl5 vl3 vl2 vl1 vl0 7* base image display control 7bh- 7fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80h partial image 1 display position 0 0 0 0 0 0 0 0 ptdp 07 ptdp 06 ptdp 05 ptdp 04 ptdp 03 ptdp 02 ptdp 01 ptdp 00 81h partial image 1 ram area (start line) 0 0 0 0 0 0 0 0 ptsa 07 ptsa 06 ptsa 05 ptsa 04 ptsa 03 ptsa 02 ptsa 01 ptsa 00 82h partial image 1 ram area (end line) 0 0 0 0 0 0 0 0 ptea 07 ptea 06 ptea 05 ptea 04 ptea 03 ptea 02 ptea 01 ptea 00 83h partial image 2 display position 0 0 0 0 0 0 0 0 ptdp 17 ptdp 16 ptdp 15 ptdp 14 ptdp 13 ptdp 12 ptdp 11 ptdp 10 84h partial image 2 ram area (start line) 0 0 0 0 0 0 0 0 ptsa 17 ptsa 16 ptsa 15 ptsa 14 ptsa 13 ptsa 12 ptsa 11 ptsa 10 85h partial image 2 ram area (end line) 0 0 0 0 0 0 0 0 ptea 17 ptea 16 ptea 15 ptea 14 ptea 13 ptea 12 ptea 11 ptea 10 8* partial image control 86h- 8fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90h panel interface control 1 0 0 0 0 0 0 divi1 divi0 0 0 0 0 rtni3 rtni2 rtni1 rtni0 91h panel interface control 2 0 0 0 0 0 noi2 noi1 noi0 0 0 0 0 0 0 0 0 92h panel interface control 3 0 0 0 0 0 0 0 0 0 0 0 0 0 sdti2 sdti1 sdti0 93h panel interface control 4 0 0 0 0 0 0 dive1 dive0 0 0 rtne5 rtne4 rtne3 rtne2 rtne1 rtne0 94h panel interface control 5 0 0 0 0 noe3 noe2 noe1 noe0 0 0 0 0 0 0 0 0 95h panel interface control 6 0 0 0 0 0 0 0 0 0 0 0 0 0 sdte2 sdte1 sdte0 96h- 97h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9* panel interface control 98h- 9fh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a0h nv memory access control 1 0 0 0 0 0 0 0 0 te 0 eop1 eop0 0 0 ead1 ead0 a1h nv memory access control 2 0 0 0 0 0 0 0 0 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 a2h-a3h setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a4h calibration control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 calb a* nv memory control a5h-afh setting disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R61503U specification rev.1.1, march 29, 2007, page 88 of 186 reset function the R61503U is initialized by the reset input. during reset period, the R61503U is in a busy state and instruction from the mpu and gram access are not accepted. the R61503U?s internal power supply circuit unit is initialized also by the reset input. the reset period must be secured for at least 1ms. in case of power-on reset, wait until the rc oscillation frequency stabilizes (for 10 ms). during this period, gram access and initial instruction setting are prohibited. 1. initial state of instruction bits (default) see the instruction list of p.86. the default value is shown in the parenthesis of each instruction bit cell. 2. ram data initialization the ram data is not automatically initialized by the reset input. it must be initialized by software in display-off period (d1-0 = ?00?). 3. output pin initial state * see note 1. lcd driver s1~s528 : gnd g1~g220 : vgl (= gnd) 2. vcom : gnd 3. vcomh : vci 4. vcoml : gnd 5. vreg1out : vgs 6. vci1 : hi-z 7. ddvdh : vci 8. vgh : ddvdh (= vci) 9. vgl : gnd 10. oscillator : oscillate 4. initial state of input/output pins* see note 1. c11+ : hi-z 2. c11- : hi-z 3. c13+ : vci1 (= hi-z) 4. c13- : gnd 5. c21+ : ddvdh ( = vci) 6. c21- : gnd 7. c22+ : ddvdh ( = vci) 8. c22- : gnd 9. vdd : vdd note: the initial states of output and input pins become the states mentioned in the above when the R61503U?s power supply circuit is connected as exemplified in ?connection example?.
R61503U specification rev.1.1, march 29, 2007, page 89 of 186 5. note on reset function a) when a reset input is entered into the R61503U while it is in deep standby mode, the R61503U starts up the inside logic regulator and makes a transition to the initial state. during this period, the state of the interface pins may become unstable. for this reason, do not enter a reset input in deep standby mode. b) when transferring instruction and data in either two or three transfers via 8-/16-bit interface, make sure to execute data transfer synchronization after reset operation.
R61503U specification rev.1.1, march 29, 2007, page 90 of 186 interface and data format the R61503U supports system interface for setting instructions etc, and external display interface for displaying a moving picture. the R61503U can select the optimum interface for the display (moving or still picture) in order to transfer data efficiently. as external display interface, the R61503U supports rgb interface and vsync interface, which enables data rewrite operation without flickering the moving picture on display. in rgb interface operation, the display operation is executed in synchronization with synchronous signals vsync, hsync, and dotclk. in synchronization with these signals, the R61503U writes display data while the data enable signal (enable) allows write operation via rgb data signal bus (db17-0). the display data is stored in the R61503U?s gram so that data is transferred only when rewriting the frames of moving picture and the data transfer required for moving picture display can be minimized. the window address function specifies the ram area to write data for moving picture display, which enables displaying a moving picture and ram data in other than the moving picture area simultaneously. to access the R61503U?s internal ram in high speed with low power consumption, use high-speed write function (hwm = 1) in rgb or vsync interface operation. in vsync interface operation, the internal display operation is synchronized with the frame synchronization signal (vsync). the vsync interface enables a moving picture display via system interface by writing the data to the gram at faster than the minimum calculated speed in synchronization with the falling edge of vsync. in this case, there are restrictions in setting the frequency and the method to write data to the internal ram. the R61503U operates in either one of the following four modes according to the state of the display. the operation mode is set in the external display interface control register. when switching from one mode to another, make sure to follow the relevant sequence in setting instruction bits.
R61503U specification rev.1.1, march 29, 2007, page 91 of 186 table 55 operation mode ram access setting (rm) display operation mode (dm1-0) internal operating clock only (displaying still picture) system interface (rm = 0) internal operating clock (dm1-0 = 00) rgb interface (1) (displaying moving picture) rgb interface (rm = 1) rgb interface (dm1-0 = 01) rgb interface (2) (rewriting still picture while displaying moving pictures) system interface (rm = 0) rgb interface (dm1-0 = 01) vsync interface (displaying moving pictures) system interface (rm = 0) vsync interface (dm1-0 = 10) notes: 1. instructions are set only via system interface. 2. the rgb and vsync interfaces cannot be used simultaneously. 3. do not make changes to the rgb interface operation setting (rim1-0) while rgb interface is in operation. 4. see the ?external display interface? section for the sequences when switching from one mode to another. 5. use high-speed write function (hwm = 1) when writing data via rgb or vsync interface. cs * rs wr * R61503U system interface 18/16/9/8 rgb interface 18/16/6 db17-0 (rd * ) enable vsync hsync dotclk system interface rgb interface system figure 19
R61503U specification rev.1.1, march 29, 2007, page 92 of 186 internal clock operation the display operation is synchronized with signals generated from internal oscillator?s clock (osc) in this mode. all input via external display interface is disabled in this operation. the internal ram can be accessed only via system interface. rgb interface operation (1) the display operation is synchronized with frame synchronous signal (vsync), line synchronous signal (hsync), and dot clock signal (dotclk) in rgb interface operation. these signals must be supplied during the display operation via rgb interface. the R61503U transfers display data in units of pixels via db17-0 pins. the display data is stored in the internal ram. the combined use of high-speed ram write mode and window address function can minimize the total number of data transfer for moving picture display by transferring only the data to be written in the moving picture ram area when it is written and enables the R61503U to display a moving picture and the data in other than the moving picture ram area simultaneously. the front porch (fp), back porch (bp), and the display (nl) periods are automatically calculated inside the R61503U by counting the number of clocks of line synchronous signal (hsync) from the falling edge of the frame synchronous signal (vsync). make sure to transfer pixel data via db17-0 pins in accordance with the setting of these periods. rgb interface operation (2) this mode enables the R61503U to rewrite ram data via system interface while using rgb interface for display operation. to rewrite ram data via system interface, make sure that display data is not transferred via rgb interface (enable = high). to return to the rgb interface operation, change the enable setting first. then set an address in the ram address set register and r22h in the index register. vsync interface operation the internal display operation is synchronized with the frame synchronous signal (vsync) in this mode. this mode enables the R61503U to display a moving picture via system interface by writing data in the internal ram at faster than the calculated minimum speed via system interface from the falling edge of frame synchronous (vsync). in this case, there are restrictions in speed and method of writing ram data. for details, see the ?vsync interface? section. as external input, only vsync signal input is valid in this mode. other input via external display interface becomes disabled. the front porch (fp), back porch (bp), and the display (nl) periods are automatically calculated from the frame synchronous signal (vsync) inside the R61503U according to the instruction settings for these periods.
R61503U specification rev.1.1, march 29, 2007, page 93 of 186 system interface the following kinds of system interface are available with the R61503U and the interface is selected by setting the im3/2/1/0 pins. the system interface is used for instruction setting and ram access. table 56 im bits settings and system interface im3 im2 im1 im0 interface operation db pins colors 0 0 0 0 setting disabled - - 0 0 0 1 setting disabled - - 0 0 1 0 80-system 16-bit interface db17-10 and db8-1 65,536, 262,144 see note 1 0 0 1 1 80-system 8-bit interface db17-10 65,536, 262,144 see note 2 0 1 0 * clock synchronous serial interface db1-0 65,536 0 1 1 * setting disabled - - 1 0 0 0 setting disabled - - 1 0 0 1 setting disabled - - 1 0 1 0 80-system 18-bit interface db17-0 262,144 1 0 1 1 80-system 9-bit interface db17-9 262,144 1 1 * * setting disabled - - notes : 1. 262,144 colors in 2 transfers, 65,536 colors in 1 transfer. 2. 262,144 colors in 3 transfers, 65,536 colors in 2 transfers.
R61503U specification rev.1.1, march 29, 2007, page 94 of 186 80-system 18-bit interface a1 hwr rs wr * 18 R61503U mpu csn * (rd * )(rd * ) d31-0 cs * db17-0 figure 20 instruction write db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db db 5 db 4 db 3 db 2 db 1 ib 15 ib ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 14 6 device code read db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db db 5 db 4 db 3 db 2 db 1 db 0 ib 15 ib ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 14 6 instruction code instruction code input instruction device code output 0 0 figure 21 instruction/device code read (18-bit interface) ram data read ram data write r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 rd [17] rd [16] rd [15] rd [14] rd [13] rd [12] rd [11] rd [10] [9] rd [8] rd [7] rd [6] rd [5] rd [4] rd [3] rd [2] rd [1] rd [0] db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 gram data read data output pins 1 pixel input gram write data normal display in 262,144 colors note: rd db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 figure 22 ram data write/read (18-bit interface)
R61503U specification rev.1.1, march 29, 2007, page 95 of 186 80-system 16-bit interface rs wr* 16 R61503U mpu im[3:0] = 0010 cs* db17-10, 8-1 (rd*) db9, 0 d15-0 csn* a1 hwr (rd*) figure 23 instruction db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db db 5 db 4 db 3 db 2 db 1 ib 15 ib ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 14 6 instruction input instruction code db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db db 5 db 4 db 3 db 2 db 1 db 0 ib 15 ib ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 14 6 instruction code device code read device code output note: device code cannot be read in 2 transfer mode. 0 0 figure 24 instruction/device code read (16-bit interface)
R61503U specification rev.1.1, march 29, 2007, page 96 of 186 ram data write (single transfer mode: tri = 0, dfm = 00) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 7 note: 65,536-color display input 1 pixel r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 ram data write (single transfer mode: tri = 0, dfm = 11) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 7 note: 65,536-color display input 1 pixel r5 r4 r3 r2 r1 1 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 1 ram data write (single transfer mode: tri = 0, dfm = 10) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 7 note: 65,536-color display input 1 pixel r5 r4 r3 r2 r1 0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 0 figure 25 ram data write (16-bit interface)
R61503U specification rev.1.1, march 29, 2007, page 97 of 186 ram data read r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 rd [17] rd [16] rd [15] rd [14] rd [13] rd [12] rd [11] rd [10] rd [9] rd [8] rd [7] rd [6] rd [5] rd [4] rd [3] rd [2] rd [1] rd [0] db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 read data output pins gram data ram data write (two transfer mode: tri = 1, dfm=0*) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 7 input db 17 16 db r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 note: 262,144-color display 1 pixel 1st transfer 2nd transfer ram data write (two transfer mode: tri = 1, dfm=1*) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db db 6 db 5 db 4 db 3 db 2 db 1 7 input db 2 1 db r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 note: 262,144-color display 1 pixel 1st transfer 2nd transfer figure 26 ram data write/read (16-bit interface)
R61503U specification rev.1.1, march 29, 2007, page 98 of 186 80-system 9-bit interface when transferring 16-bit instruction via 9-bit interface (db17~db9), it is divided into upper and lower 8 bits (db9 is not used) and the upper 8 bits are transferred first. the ram write data is divided into upper and lower 9 bits and the upper 9 bits are transferred first. the unused db8-0 pins must be fixed at either iovcc or gnd level. when writing in the index register, make sure to write the upper byte (8 bits). a1 hwr rs wr * 9 9 R61503U h8/2245 csn * (rd * )(rd * ) d15-0 cs * db17-9 db8-0 figure 27 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 ib 15 ib ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 14 instruction write input instruction first transfer second transfer instruction code db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 ib 15 ib ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 14 first transfer second transfer device code read instruction output instruction code figure 28 instruction/device code read (9-bit interface)
R61503U specification rev.1.1, march 29, 2007, page 99 of 186 ram data read ram data write r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 rd [17] rd [16] rd [15] rd [14] rd [13] rd [12] rd [11] rd [10] [9] rd [8] rd [7] rd [6] rd [5] rd [4] rd [3] rd [2] rd [1] rd [0] db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db db db db db db db db db gram data read data output pins 1 pixel input gram write data 262,144-color display note: rd db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db db db db db db db db db r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9 1st transfer 2nd transfer 1st transfer 2nd transfer figure 29 ram data write/read (9-bit interface) the R61503U supports data transfer synchronization function to reset the counters, which count the number of upper and lower 9 bits when transferring data via 9-bit bus interface. if a mismatch occurs in transferring upper and lower 9 bits due to noise and so on, ?00?h instruction is written 4 times consecutively to reset the counters so that data transfer can resume from upper 9 bits from the next frame. the synchronization function, when executed periodically, can prevent the runaway operation of the display system. db 17~9 upper lower ?00? h ?00? h ?00? h ?00? h upper lower upper wr rd rs (9-bit transfer synchronization) figure 30 data transfer synchronization (9-bit) make sure to execute transfer synchronization after reset operation, when starting instruction bit transfer.
R61503U specification rev.1.1, march 29, 2007, page 100 of 186 80-system 8-bit interface when transferring 16-bit instruction via 8-bit interface (db17~db10), it is divided into upper and lower 8 bits and the upper 8 bits are transferred first. the ram write data is divided into upper and lower 8 bits and the upper 8 bits are transferred first. the unused db9-0 pins must be fixed at either iovcc or gnd level. when writing in the index register, make sure to write the upper byte (8 bits). a1 hwr h8/2245 cs * rs wr * R61503U 8 10 csn * (rd *) (rd *) d15-0 db17-10 db9-0 figure 31 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 instruction write input instruction instruction code first transfer second transfer ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 device code read instruction input first transfer second transfer figure 32 instruction/device code read (8-bit interface) note: data cannot be read in 3-transfer mode.
R61503U specification rev.1.1, march 29, 2007, page 101 of 186 first transfer second transfer ram data write (2-transfer mode: tri = 00) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db db db db db db db db r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 note: 65,536-color display input 1 pixel 17 16 15 14 13 12 11 10 first transfer second transfer ram data write (2-transfer mode: tri = 11) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db db db db db db db db r5 r4 r3 r2 r1 1 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 1 note: 65,536-color display input 1 pixel 17 16 15 14 13 12 11 10 first transfer second transfer ram data write (2-transfer mode: tri = 10) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db db db db db db db db r5 r4 r3 r2 r1 0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 0 note: 65,536-color display input 1 pixel 17 16 15 14 13 12 11 10 figure 33 ram data write (8-bit interface)
R61503U specification rev.1.1, march 29, 2007, page 102 of 186 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 ram data write (3-transfer mode: tri = 1, dfm =0*) input gram data write first transfer second transfer third transfer db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 ram data write (3-transfer mode: tri = 1, dfm = 1*) input gram data write 1 pixel first transfer second transfer third transfer note: normal display in 262,144 colors db 17 db 16 db 15 db 14 db 13 db 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1 pixel note: normal display in 262,144 colors r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 ram data read r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 rd [17] rd [16] rd [15] rd [14] rd [13] rd [12] rd [11] rd [10] [9] rd [8] rd [7] rd [6] rd [5] rd [4] rd [3] rd [2] rd [1] rd [0] db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db db db db db db db db gram data read data output pins rd 17 16 15 14 13 12 11 10 1st transfer 2nd transfer figure 34 ram data write/read (8-bit interface) note: data cannot be read in 3-transfer mode.
R61503U specification rev.1.1, march 29, 2007, page 103 of 186 the R61503U supports data transfer synchronization function to reset the counters, which count the number of upper and lower 8 bits when transferring data via 8-bit bus interface. if a mismatch occurs in transferring upper and lower 8 bits due to noise and so on, ?00?h instruction is written 4 times consecutively to reset the counters so that data transfer can resume from upper 8 bits from the next frame. the synchronization function, when executed periodically, can prevent the runaway operation of the display system. db 17~10 upper lower ?00? h ?00? h ?00? h ?00? h upper lower upper wr rd rs (8-bit transfer synchronization) figure 35 data transfer synchronization (8-bit) make sure to execute transfer synchronization after reset operation, when starting instruction bit transfer.
R61503U specification rev.1.1, march 29, 2007, page 104 of 186 serial interface the serial interface is selected by setting the im3/2/1 pins to gnd/iovcc/gnd levels, respectively. the data is transferred via chip select line (cs), serial transfer clock line (scl), serial data input line (sdi), and serial data output line (sdo). in serial interface operation, the im0/id pin functions as the id pin, and the db17-0 pins, not used in this mode, must be fixed at either iovcc or gnd level. the R61503U recognizes the start of data transfer on the falling edge of cs input and starts transferring the start byte. it recognizes the end of data transfer on the rising edge of cs input. the R61503U is selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit device identification code assigned to the R61503U are compared and both 6-bit data match. then, the R61503U starts taking in subsequent data. the least significant bit of the device identification code is determined by setting the id pin. send "01110? to the five upper bits of the device identification code. two different chip addresses must be assigned to the R61503U because the seventh bit of the start byte is register select bit (rs). when rs = 0, either index register write or status read operation is executed. when rs = 1, either instruction write operation or ram read/write operation is executed. the eighth bit of the start byte is r/w bit, which selects either read or write operation. the R61503U receives data when the r/w = 0, and transfers data when the r/w = 1. when writing data to the gram via serial interface, the data is written to the gram after it is transferred in two bytes. the R61503U writes data to the gram in units of 18 bits by adding the same bits as the msbs to the lsb of r and b dot data. after receiving the start byte, the R61503U starts transferring or receiving data in units of bytes. the R61503U transfers data from the msb. the R61503U?s instruction consists of 16 bits and it is executed inside the R61503U after it is transferred in two bytes (16 bits: db15-0) from the msb. the R61503U expands ram write data into 18 bits when writing them to the internal gram. the first byte received by the R61503U following the start byte is recognized as the upper eight bits of instruction and the second byte is recognized as the lower 8 bits of instruction. when reading data from the gram, valid data is not transferred to the data bus until first five bytes of data are read from the gram following the start byte. the R61503U sends valid data to the data bus when it reads the sixth and subsequent byte data. table 57 start byte format transferred bits s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 0 1 1 1 0 id note: the id bit is selected by setting the im0/id pin.
R61503U specification rev.1.1, march 29, 2007, page 105 of 186 table 58 rs r/w function 0 0 set index register 0 1 read status 1 0 write instruction or ram data 1 1 read instruction or ram data instruction first transfer (upper) second t ransfer (lower) input d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 instruction ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 instruction co de ram data write first transfer (upper) second tr ansfer (lower) input d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 gram write data r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b5 1pixel 65,536 colors d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 figure 36 instruction /ram data write (serial interface)
R61503U specification rev.1.1, march 29, 2007, page 106 of 186 cs* (input) scl (input) sdi (input) b)consecutive data transfer via serial interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 lsb d15 rs rw id ?0? ?1? ?1? ?1? ?0? rs rw device id code start byt e index register set, instructions, ram data write status read, instruction read, ram data read msb sdo (output) sdi (input) scl (input) cs* (input) start data transfer d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a)basic data transfer via serial interface end star t start byte rs = 1, r/w = 1 ram read lower 8 bit s c) ram data read transfer cs* (input) scl (input) sdi (input) sdi (output) note: invalid data is sent to the data bus until 5th bytes are read out from the internal gram. valid data is sent to the data bus when the 6th and subsequent bytes are read from the internal gram. end of data transfer ram read upper 8 bits dummy read (1) dummy read (2) dummy read (3) dummy read (4) dummy read (5) start end start byte instruction (1) upper 8 bits instruction (1) lower 8 bits instruction (2) upper 8 bits instruction (2) lower 8 bits execution time of instruction (1) note: the start byte is followed by upper 8 bits of instruction. end star t d) status read/instruction read note: at first, invalid data is read out when first one byte is transferred following the start byte. valid data is sent when the 2nd and subsequent bytes are transferred. start byte rs=0, r/w=1 dummy read (1) status read upper 8 bits status read lower 8 bits cs* (input) scl (input) sdi (input) sdi (output) figure 37 serial interface data transfer timing
R61503U specification rev.1.1, march 29, 2007, page 107 of 186 vsync interface the R61503U supports vsync interface, which enables displaying a moving picture via system interface by synchronizing the display operation with the vsync signal. vsync interface can realize moving picture display with minimum modification to the conventional system operation. rs wr* 18 R61503U vsync cs* db17-0 lcdc/mpu figure 38 vsync interface the vsync interface is selected by setting dm1-0 = 10 and rm = 0. in vsync interface operation, the internal display operation is synchronized with the vsync signal. by writing data to the internal ram at faster than the calculated minimum speed (internal display operation speed + margin), it becomes possible to rewrite the moving picture data without flickering the display and display a moving picture via system interface. the display operation is performed in synchronization with the internal clock signal generated from the internal oscillator and the vsync signal. the display data is written in the internal ram so that the R61503U rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display. by writing data using high-speed write function (hwm =1), the R61503U can write data via vsync interface in high speed with low power consumption. vsync ram data write via system interface internal clock note: use high-speed write function (hwm=1) when writing data via vsync interface. rewrite frame data rewrite frame data figure 39 moving picture data write via vsync
R61503U specification rev.1.1, march 29, 2007, page 108 of 186 the vsync interface has the minimum for ram data write speed and internal clock frequency, which must be more than the values calculated from the following formulas, respectively. internal clock frequency (fosc) [hz] = frame frequency (display lines (nl) + front porch (fp) + back porch (bp)) clocks per line (rtni) ram write speed (min.) [hz] > 176 display lines (nl) / ((back porch (bp) + display lines (nl) ? margins) clocks per line (rtni) 1 / fosc) note: when ram write operation is not started right after the falling edge of vsync, the time from the falling edge of vsync until the start of ram write operation must also be taken into account. an example of calculating minimum ram writing speed and internal clock frequency in vsync interface operation is as follows. [example] display size 176 rgb 220 lines display lines 220 lines back/front porch 14/2 lines (bp = 1110/ fp = 0010) frame frequency 60 hz clocks per line 16 clocks internal clock frequency (fosc) [hz] = 60 hz (220 + 2 + 14) lines 16 clocks / 0.9 1.1 = 277 khz notes: 1. when setting the internal clock frequency, possible causes of fluctuation must also be taken into consideration. in this example, the internal clock frequency allows for a margin of 10% for variances and guarantees that display operation is completed within one vsync cycle. 2. this example includes variances attributed to lsi fabrication process and room temperature. other possible causes of variances, such as differences in external resistors and voltage change are not considered in this example. it is necessary to include a margin for these factors. minimum speed for ram writing [hz] > 176 220 / {((14 + 220 - 2) lines 16 clocks) / 277 khz} = 2.89 mhz notes: 1. in this example, it is assumed that the R61503U starts writing data in the internal ram on the falling edge of vsync. 2. there must at least be a margin of 2 lines between the line to which the R61503U has just written data and the line where display operation on the lcd is performed. in this example, the ram write operation at a speed of 2.89mhz or more, which starts on the falling edge of vsync, guarantees the completion of data write operation in a certain line address before the R61503U starts the display operation of the data written in that line and moving picture data can be written without causing flicker on the display.
R61503U specification rev.1.1, march 29, 2007, page 109 of 186 ram write display operation 0 16.67 (60 hz) back porch (14 lines) main panel moving picture display (220 lines) front porch (2 lines) blank period rc oscillation 10% display operation vsync [line] 220 vsync bp = 14h ram write 2.89mhz [ms] line processing display operation figure 40 write/display operation timing via vsync interface notes to vsync interface operation 1. the above example of calculation gives a theoretical value. possible causes of variances of internal oscillator should be taken into consideration. make enough margins in setting ram write speed for vsync interface operation. 2. the above example shows the values when writing over the full screen. extra margin will be created if the moving picture display area is smaller than that. 0 16.74 (60 hz) display operation 16 back porch (14 lines) base image moving picture display (188 lines) front porch (2 lines) (16 lines) (16 lines) ram write [line] [ms] 220 188 bp = 14h vsync rc oscillation 10% display operation ram write 3.15mhz (35200 times) line processing display operation figure 41 ram write speed margin 3. the front porch period continues from the end of one frame period to the next vsync input. 4. the instructions to switch from internal clock operation (dm1-0 = 00) to vsync interface operation modes and vice versa are enabled from the next frame period.
R61503U specification rev.1.1, march 29, 2007, page 110 of 186 5. the partial display and vertical scroll functions and interlaced scan are not available in vsync interface operation. 6. in vsync interface operation, set am = 0 to transfer display data correctly. 7. in vsync interface operation, use high-speed write function (hwm = 1) when writing display data to the internal ram. hwm = 1 and am = 0 ram address set set dm1-0 = 10 and rm = 0 for vsync interface mode write data to ram via vsync interface wait one frame period or more internal clock operation to vsync interface set dm1-0=00 and rm=0 for internal clock operation wait one frame period or more internal clock operation display operation in synchronization with internal clocks *c hanges in the dm1-0 and rm bits (to vsync interface mode) are enabled from the next frame. display operation in synchronizaion with vsync set index register to r22h operation via vsync interface vsync interface to internal clock operation note: input the vsync signal before setting the dm1-0 and rm bits to vsync interface mode. operation via vsync interface internal clock operation display operation in synchronization with internal clock *c hanges in the dm1-0 and rm bits (to internal clock operation mode) are enabled from the next frame. display operation in synchronizaion with vsync note: continue the vsync signal for at least one frame period after setting dm1-0 and rm bits to internal clock operation mode. figure 42 sequence to switch between vsync and internal clock operation modes
R61503U specification rev.1.1, march 29, 2007, page 111 of 186 external display interface the R61503U supports the rgb interface. the interface format is set by rm[1:0] bits. the internal ram is accessible via rgb interface. table 59 rim1 rim0 rgb interface db pin 0 0 18-bit rgb interface db17-0 0 1 16-bit rgb interface db17-13, db11-1 1 0 6-bit rgb interface db17-12 1 1 setting disabled - note: using more than one rgb interface at a time is prohibited. rgb interface the display operation via rgb interface is synchronized with vsync, hsync, and dotclk. the data can be written only within the specified area with low power consumption by using window address function and high-speed write mode (hwm = 1). in rgb interface operation, front and back porch periods must be made before and after the display period.
R61503U specification rev.1.1, march 29, 2007, page 112 of 186 vsync 1. the front porch period continues until next vsync input is detected. 2. make sure the frequencies of vsync, hsync, and dotclk can guarantee the resolution required for the panel. 3. keep dotclk input throughout the rgb interface operation. moving picture display area display period (nl4-0) back porch period (bp3-0) front porch period (fp3-0) notes: back porch period (bpp): front porch period (fpp): display period: the number of lines for one frame: 14h ? bp ? 2h 14h ? fp ? 2h fpp + bpp = 16h nl ? 220h fpp + nl + bpp vsync: frame synchronization signal hsync: line synchronization signal dotclk: dot clock enable: data enable signal db 17-0: rgb (6:6:6) display data hsync dotclk enable (h) db17-0 figure 43 enable signal function the following table shows the relationship between the enable, epl setting and ram access operation. enable signal does not accompany address change in writing data although enable must be ?low?. epl controls the active polarity of enable signal. table 60 epl enable ram write ram address 0 0 enable update 0 1 disenable retain 1 0 disenable retain 1 1 enable update
R61503U specification rev.1.1, march 29, 2007, page 113 of 186 rgb interface timing signal timing chart of 16/18-bit rgb interface 1h 1 clock vlw = 1h or more one frame back porch period front porch period hlw ? 1clk dtst ? 1clk vsync hsync dotclk enable db17-0 vsync hsync dotclk enable db17-0 valid data figure 44 notes: 1. vlw: vsync ?low? period hlw: hsync ?low? period dtst:data transfer setup time 2. use high-speed write function (hwm = ?1?) when writing data via rgb interface.
R61503U specification rev.1.1, march 29, 2007, page 114 of 186 timing chart of signals in 6-bit rgb interface operation db17-12 vlw = 1h or more 1h 1clk r g b r g b r g b r g b r g b r g b r g b hlw ? 3clk dtst ? 3clk vsync hsync dotclk enable db17-12 vsync hsync dotclk enable one frame back porch period front porch period valid data figure 45 notes: 1. vlw: vsync ?low? period hlw: hsync ?low? period dtst:data transfer setup time 2. use high-speed write function (hwm = ?1?) when writing data via rgb interface. 3. in 6-bit rgb interface operation, set the cycles of vsync, hsync, enable, dotclk so that one pixel data is transferred in units of three clocks via db17-12.
R61503U specification rev.1.1, march 29, 2007, page 115 of 186 moving picture display via rgb interface the R61503U supports rgb interface for moving picture display and incorporates ram for storing display data, which provides the following advantages in displaying a moving picture. 1. the window address function enables transferring data only within the moving picture area 2. the high-speed write function enables ram access in high speed with low power consumption 3. it becomes possible to transfer only the data written over the moving picture area 4. by reducing data transfer, it can contribute to lowering the power consumption of the whole system 5. the data in still picture area (icons etc.) can be written over via system interface while displaying a moving picture via rgb interface ram access via system interface in rgb interface operation the R61503U allows ram access via system interface in rgb interface operation. in rgb interface operation, data is written to the internal ram in synchronization with dotclk while enable is ?low?. when writing data to the ram via system interface, set enable ?high? to stop writing data via rgb interface. then set rm = ?0? to enable ram access via system interface. when reverting to the rgb interface operation, wait for the read/write bus cycle time. then, set rm = ?1? and the index register to r22h to start accessing ram via rgb interface. if there is a conflict between ram accesses via two interfaces, there is no guarantee that the data is written in the ram. the following is an example of rewriting still picture data via system interface while displaying a moving picture via rgb interface.
R61503U specification rev.1.1, march 29, 2007, page 116 of 186 index r2 2 ram address set rewrite data outside the moving picture ram area rm= 1 index r2 2 rewrite moving picture area 2004/01/01 00:00 2 0 0 4 / 0 1 / 0 1 0 0 : 0 0 frame rewrite rewrite still picture ram address set frame rewrite rewrite moving picture area note 1) in rgb interface operation, ram address (ad16-0) is set in the address counter on the falling edge of vsync. note 2) set a ram address (ad16-0) and the index to r22h before starting ram access via rgb interface. note 3) use high-speed write function (hwm = "1") when writing data via rgb interface. note 2) moving picture area vsync enable dotclk db17-0 system interface rm=0 figure 46 updating a still picture area while displaying a moving picture
R61503U specification rev.1.1, march 29, 2007, page 117 of 186 6-bit rgb interface the 6-bit rgb interface is selected by setting the rim1-0 bits to 10. the display operation is synchronized with vsync, hsync, and dotclk signals. the display data is transferred to the internal ram in synchronization with the display operation via 6-bit rgb data bus (db17-12) while the data enable signal (enable) allows ram access via rgb interface. unused pins (db11 to 0) must be fixed at either iovcc or gnd level. instruction bits can be transferred only via system interface. 6 12 R61503U db17-12 vsync hsync dotclk enable lcdc db11-0 db db db db db db db db db db db db db db db db db db 1 pixel data format for the 6-bit rgb interface (rim = 10) input gram write data first transfer second transfer third transfer note: 262,144 colors r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 rim = 01 figure 47 6-bit rgb interface and data format
R61503U specification rev.1.1, march 29, 2007, page 118 of 186 data transfer synchronization in 6-bit rgb interface operation the R61503U has the counters, which count the first, second, third 6 bit transfers via 6-bit rbg interface. the counters are reset on the falling edge of vsync so that the data transfer will start from the first 6 bits of 18-bit rgb data from the next frame period. accordingly, the data transfer via 6-bit interface can restart in correct order from the next frame period even if a mismatch occurs in transferring 6-bit data. this function can minimizes the effect from data transfer mismatch and help the display system return to normal display operation when data is transferred consecutively in moving picture operation. make sure the internal display operation within the R61503U is performed in units of pixels and input 3 dotclk to transfer one pixel data (rgb) via 6-bit interface. if the number of dotclk inputted in one frame period does not satisfy this condition, data transfer mismatch will occur and its effect will be carried over to the next frame. db17-12 vsync enable dotclk second transfer second transfer second transfer first transfer first transfer third transfer third transfer transfer synchronization figure 48 6-bit transfer synchronization
R61503U specification rev.1.1, march 29, 2007, page 119 of 186 16-bit rgb interface the 16-bit rgb interface is selected by setting the rim1-0 bits to ?01?. the display operation is synchronized with vsync, hsync, and dotclk signals. the display data is transferred to the internal ram in synchronization with the display operation via 16-bit rgb data bus (db17-10, db8-1) while data enable signal (enable) allows ram access via rgb interface. instruction bits can be transferred only via system interface. lcdc 16 2 input db 17 db 16 db 15 db 14 db 13 db 9 db 10 db 11 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db17-13, 11-1 db12,0 vsync hsync dotclk enable R61503U rim = 01 data format for the16-bit interface (rim = 01) r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1 pixel gram write data figure 49 16-bit rgb interface and data format
R61503U specification rev.1.1, march 29, 2007, page 120 of 186 18-bit rgb interface the 18-bit rgb interface is selected by setting the rim1-0 bits to ?00?. the display operation is synchronized with vsync, hsync, and dotclk signals. the display data is transferred to the internal ram in synchronization with the display operation via 18-bit rgb data bus (db17-0) while data enable signal (enable) allows ram access via rgb interface. instruction bits can be transferred only via system interface. vsync R61503U 18 hsync dotclk enable db17-0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 rim = 00 data format for the 18-bit interface (rim = 00) input gram write data 1 pixel note: normal display in 262,144 colors r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 lcdc figure 50 18-bit rgb interface and data format
R61503U specification rev.1.1, march 29, 2007, page 121 of 186 notes to external display interface operation 1. the following functions are not available in external display interface operation. table 61 functions not available in external display interface operation function external display interface internal clock operation partial display not available available scroll function not available available interlaced scan not available available 2. the vsync, hsync, and dotclk signals must be supplied during display period. 3. the reference clock, which is used for determining the periods set by noe[1:0], stde[1:0] bits in rgb interface operation is dotclk, not the internal clock generated from the internal oscillator. 4. in 6-bit rgb interface operation, 6-bit dot data (r, g, and b) is transferred in synchronization with dotclk. in other words, it takes three dotclks to transfer one pixel data. 5. in 6-bit rgb interface operation, make sure to set the cycles of vsync, hsync, dotclk, enable signals so that the data transfer via db17-12 is completed in units of pixels. 6. when switching between the internal operation mode and the external display interface operation mode, follow the sequences below in setting instruction. 7. in rgb interface operation, a front porch period continues after the end of frame period until next vsync input is detected. 8. in rgb interface operation, use high-speed write function (hwm = 1) when writing data to gram. 9. in rgb interface operation, ram address ad15-0 is set in the address counter every frame on the falling edge of vsync.
R61503U specification rev.1.1, march 29, 2007, page 122 of 186 internal clock operation to rgb interface (1) operation via rgb interface rgb interface (1) to internal clock operation internal clock operation hwm = 1 and am = 0 ram address set set dm1-0 = 01 and rm = 1 for rgb interface write data to ram via rgb interface wait one frame period or more set index register to r22h display operation in synchronization with internal clocks rgb interface operation display operation in synchronization with vsync, hsync, and dotclk display operation in synchronization with vsync, hsync, and dotclk internal clock operation set internal clock operation mode * (dm1-0 = 00 and rm = 0) display operation in synchronization with internal clocks note: continue rgb interface signals at least for one frame period after setting dm1-0, rm bits to internal clock operation mode. note: input the rgb interface signals before setting the dm1-0 and rm bits to rgb interface. * changes in the dm1-0, rm bits (set the rgb interface mode) are enebled from the next frame. * changes in the dm1-0, rm bits (set the internal clock mode) are enebled from the next frame wait one frame period or more figure 51 rgb interface operation and internal clock operation transition
R61503U specification rev.1.1, march 29, 2007, page 123 of 186 ram address and display position on the panel the R61503U has memory to store the display data of 176rgb x 220 lines. the R61503U incorporates a circuit to control partial display, which allows switching the display driving mode between full-screen display mode and partial display mode. the R61503U makes the display design setting and the panel driving position control setting separately and specifies the ram area for each image displayed on the panel. for this reason, there is no need to take the mounting position of the panel into consideration when designing a display on the panel. the following is the sequence of setting full-screen and partial display. 1. set (ptsax, pteax) to specify the ram area for each partial image 2. set the display position of each partial image on the base image by setting ptdpx. 3. set nl to specify the number of lines to drive the liquid crystal panel to display the base image 4. after display on, set display enable bits (basee, ptde0/1) to display respective images normal display basee = 1 partial display basee = 0, ptde0/1 = 1 5. change basee, ptde0/1 setting to switch display modes (full-screen and partial display modes). in driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface in accordance with the number of lines to drive the liquid crystal panel (nl setting). when switching the display position in horizontal direction, set ss bit when writing ram data. table 62 display enable numbers of lines ram area base image basee nl (bsa, bea) = (8?h00, 8?hdb) notes 1: the base image is displayed from the first line of the panel. 2: make sure nl 220 (lines) = bea ? bsa when setting a base image ram area. bsa and bea are fixed to 8?h00, 8?hdb, respectively. table 63 display enable display position ram area partial image 1 ptde0 ptdp0 (ptsa0, ptea0) partial image 2 ptde1 ptdp1 (ptsa1, ptea1)
R61503U specification rev.1.1, march 29, 2007, page 124 of 186 bsa bea base im age (hsa,hea) (vsa,v ea) window address base image ram address ram write addr ess ptdp0 partial image 1 panel display position 1 nl lcd ptsa0 ptea0 partial image ram address gate line scan direction partial image 2 ptsa1 ptea1 ptdp1 display data output position figure 52 ram address, display position and drive position restrictions in setting display control instruction partial image display set the partial image ram area setting registers (ptsax, pteax bits) and the partial position setting registers (ptdpx bits) so that the ram areas and the display positions of partial images do not overlap one another. 0 ptdp0 ptdp0+ (ptea0 - ptsa0) < ptdp1 ptdp1+ (ptea1 - ptsa1) nl
R61503U specification rev.1.1, march 29, 2007, page 125 of 186 the following figure shows the relationship among the ram address, display position, and the lines driven for the display. 0 lcd panel physical line address 0 (1st line) 3 1 (2nd line) 2 (3rd line) nl display panel ram line address bsa = 8'h00 n-1 (n lines) nl ptdp0 osd image 1 display area ptdp1 1 2 4 5 nl display data output order osd image 2 display area base image ram area figure 53 display ram address and panel display position note: this figure shows the relationship between ram line address and the display position on the panel. in the R61503U?s internal operation, the data is written in the ram area specified by the window address setting (hea/hsa[7:0], vea/ves[8:0]).
R61503U specification rev.1.1, march 29, 2007, page 126 of 186 instruction setting example the followings are examples of display design setting for 176(rgb) x 220(lines) panels. 1. full screen display (no partial) the following is an example of full screen display setting. table 64 base image display instruction basee 1 nl[4:0] 5?h14 ptde0 0 ptde1 0 3 nl (220 lines) 219 ( 22 0th line) 1 2 4 5 220 9?h000 bsa=8'h00 bea = 8?hdb lcd panel physical line address 0 (1st line) 1 (2nd line) 2 (3rd line) ram line address display data output order base image ram area base image figure 54 full screen display (no partial)
R61503U specification rev.1.1, march 29, 2007, page 127 of 186 2. partial only the following is an example of setting for partial image 1 only and turning off the base image. the partial image 1 is displayed at the position specified by ptdp0 bit. table 65 base image display instruction basee 0 nl[4:0] 5?h14 partial image 1 display instruction partial image 2 display instruction ptde0 1 ptde1 0 ptsa0[7:0] 8?h00 ptsa1[7:0] 8?h00 ptea0[7:0] 8?h0f ptea1[7:0] 8?h00 ptdp0[7:0] 8?h80 ptdp1[7:0] 8?h00 3 nl (220 lines) 219 ( 220 0th line) 1 2 4 5 220 bea = 8?hdb ptsa0=8'00 ptea0=8'0f ptdp0 partial image display area base image (non-lit display level) lcd panel physical line address 0 (1st line) 1 (2nd line) 2 (3rd line) ram line address display data output order base mage ram area partial image 1 ram area figure 55 partial display
R61503U specification rev.1.1, march 29, 2007, page 128 of 186 high-speed ram write function the R61503U supports high-speed ram write function to write data to each line of window address area at a time. this function makes the R61503U available with the applications, which require high-speed, low- power-consumption data write operation such as color moving picture display. when enabling high-speed ram write function (hwm = ?1?), the data is first stored in the internal register of the R61503U in order to rewrite the ram data in each horizontal line of the window address area at a time. also, when transferring the data from the internal register to the internal ram, the data written in the next line of the window address area can be transferred to the internal register of the R61503U. the high- speed write function minimizes the number of ram access in write operation and enables high-speed consecutive ram write operation required for moving picture display with low power consumption. microcomputer gram address counter (a c) 18 18 x n 17 register 1 register 2 register n ............... ........... 17'h00000 17'h00001 17'h00003 latch circuit figure 56 high-speed ram write operation 1 2 n 1 2 n 1 2 n 17?h00000 ? 17?h0000n 17?h00200 ? 17?h0020n 17?h0100 ? 17?h010n (1) (2) (n) (1) (2) (n) (1) (2) (n) (1) - (n) (2n+1) - (3n) (n+1) - (2n) ram write data (18 x n bits) ram address (ad17-0) ram data index (r22) index (r22) cs (input) wr (input) db17-0 (input) ram write execution time ram write execution time ram write execution time x 2 (see note) ram data ram data ram data figure 57 high-speed ram write operation timing relationship note: when switching from high-speed ram write operation to index write operation, wait at least for 2 bus cycle periods (2 x t cycw ) for normal ram write operation before executing next instruction.
R61503U specification rev.1.1, march 29, 2007, page 129 of 186 17?h00000 ? 17?h0000n 17?h00100 ? 17?h0010n (1) ?(n) (n+1) ? (2n) 1 2 2n-1 n 1 2 2n-1 n ram address (ad16-0) ram write data (18 x n bits) ram write execution time ram write execution time cs (input) wr (input) db17-0 (input) ram data ram data index (r22) ram data upper (1) ram data lower (1) ram data upper (n) ram data upper (n) ram data upper (1) ram data lower (1) ram data lower (n) ram data lower (n) figure 58 high-speed ram write operation via 9-bit interface note: in high-speed ram write operation, the R61503U writes data in units of n words. when using 9- bit interface, the R61503U performs write operation 2 x n times in the internal register before writing the data in each line of the window address area. notes to high-speed ram write function 1. in high-speed ram write mode, the R61503U performs write operation to the internal ram in units of lines. if the data inputted to the internal write register is not enough to rewrite the data in the horizontal line of the window address area, the data is not written correctly in that line address. 2. if the ir is set to 22h when hwm = ?1?, the R61503U always performs ram write operation. with this setting, the R61503U does not perform ram read operation. make sure to set hwm = 0, when performing ram read operation. 3. the high-speed ram write function cannot be used when writing data in normal ram write function mode. when switching form one write mode to the other, change the mode first and set ad16-0 (ram address set) before starting write operation.
R61503U specification rev.1.1, march 29, 2007, page 130 of 186 table 66 normal ram write (hwm=0) high-speed ram write (hwm=1) bgr function available available ram address set in units of words in units of words ram read in units of words not available ram write in units of words in units of horizontal lines window address in units of words (minimum window address area: 1 word x 1 line) in units of words (minimum window address area: 8 words x 1 line) am am = 1/0 am = 0 high-speed ram data write in a window address area the R61503U can perform consecutive high-speed data rewrite operation within a rectangular area (minimum: 8 words x 1 line) made in the internal ram with the following settings. when writing data to the internal ram using high-speed ram write function, make sure each line of the window address area is overwritten at a time. if the data buffered in the internal register of the R61503U is not enough to overwrite the horizontal line in the window address area, the data is not written correctly in that line. the following is an example of writing data in the window address area using high-speed write function when a window address area is made by setting hsa = 8?h12, hea = 8?ha7, vsa = 9?h020, vea = 9?h05b. window address area gram addr ess map window address area hsa = 8'h12, hea = 8'ha7 vsa = 9'h020,vea = 9'h05b write in horizontal direction am = 0, i/d0 = 1 window address setting area enable high speed ram write hw m = 1 ram address set ad = ram write x 150 times x 60 times note: set a ram address within the window address area. (data rewrite area) hsa = 8'h12, hea = 8'ha7 vsa = 9'h020, vea = 9'h05b 17'h02012* see note 17'h00000 17'h05ba7 17h'02012 17?h0dbaf figure 59
R61503U specification rev.1.1, march 29, 2007, page 131 of 186 window address function the window address function enables writing display data consecutively in a rectangular area (a window address area) made in the internal ram. the window address area is made by setting the horizontal address register (start: hsa7-0, end: hea 7-0 bits) and the vertical address register (start: vsa8-0, end: vea8-0 bits). the am and i/d bits set the transition direction of ram address (either increment or decrement, horizontal or vertical, respectively). setting these bits enables the R61503U to write data including image data consecutively without taking the data wrap position into account. the window address area must be made within the gram address map area. also, the ad16-0 bits (ram address set register) must be set to an address within the window address area. [window address area] (horizontal direction) 8?h00 hsa hea 8?haf (vertical direction) 9?h000 vsa vea 9?h0db [ram address (ad16-0)] (ram address) hsa ad7-0 hea vsa ad16-8 vea window address area gram address map 17'h00000 17'h000af 17'h0db00 17'h0dbaf 17'h02010 17'h02110 17'h05f10 17'h0212f 17'h0202f 17'h05f2f hsa = 8'h10, hea = 8'h2f i/d = 2'h3 (increment) vsa = 9'h020, vea = 9'h05f am = 1'h0 (horizontal writing) window address area figure 60 automatic address update within a window address area
R61503U specification rev.1.1, march 29, 2007, page 132 of 186 scan mode setting the R61503U allows for changing the gate-line/gate driver assignment and the shift direction of gate line scan in the following 4 different ways by combination of sm and gs bit settings. these combinations allow various connections between the R61503U and the lcd panel.
R61503U specification rev.1.1, march 29, 2007, page 133 of 186 sm 0 1 176 220 r6150 3b 220 219 218 217 2 1 4 3 176 220 r61503 b 2 1 4 3 220 219 218 217 176 220 r61503b 220 219 111 112 110 1 2 109 176 220 r61503b 1 2 110 109 111 220 112 219 scan direction interchanging forward direction (gs = 0) interchanging backward direction (gs = 1) left/right forward direction (gs = 0) left/right backward direction (gs = 1) note: the numbers in the circles in the figure show the order of scan. main panel (gs0) main panel (gs1) main panel (gs1) main panel (gs0) (non-bump view) (non-bump view) (non-bump view) (non-bump view) scan order (gate line no.) scan order (gate line no.) scan order (gate line no.) scan order (gate line no.) g1 e g2 e g3 e g4... g217 e g218 e g219 e g220 g220 e g219 e g218 e g217... g4 e g3 e g2 e g0 g1 e g3...g217 e g219 e g2 e g4...g218 e g220 g220 e g218... g4 e g2 e g219 e g217... g3 e g1 figure 61
R61503U specification rev.1.1, march 29, 2007, page 134 of 186 8-color display mode the R61503U has a function to display in eight colors. in this display mode, only v0 and v31 are used and power supplies to other grayscales (v1 to v30) are turned off to reduce power consumption. in 8-color display mode, the -adjustment registers p0kp0-p0kp5, p0kn0-p0kn5, p0rp0, p0rp1, p0rn0, p0rn1 are disabled and the power supplies to v1 to v30 are halted. the R61503U does not require gram data rewrite for 8-color display by writing the msb to the rest in each dot data to display in 8 colors. 2 lcd driver r g b lcd v31 v0 b 5 g 5 r 5 r 5 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 5 b 4 b 3 b 2 b 1 b 0 display data gram msb l sb lcd driver lcd driver grayscale amplifier two-level grayscale control two-level grayscale control two-level grayscale control figure 62
R61503U specification rev.1.1, march 29, 2007, page 135 of 186 n-line inversion ac drive the R61503U, in addition to the frame-inversion liquid crystal alternating current drive, supports the n-line inversion alternating current drive to invert the polarity of liquid crystal in every n-line periods, where n takes a number from 1 to 64. the n-line inversion can provide a solution when there is a need to improve the display quality. frame-inversion ac drive 220 line drive line inversion ac drive back porch front porch back porch front porch 1 2 3 4 1 2 3 4 221222 221 222 236 236 220 line drive line inversion eor = 1 one frame one frame notes: 1. make sure to set eor = ?1? to prevent direct bias on liquid crystal when selecting n-line inversion drive. 2. the n-line inversion is halted in blank period (back, front porch periods) and restarted at the first line of the display area. figure 63
R61503U specification rev.1.1, march 29, 2007, page 136 of 186 alternating timing the following figure illustrates the liquid crystal polarity inversion timing in different lcd driving methods. in case of frame-inversion ac drive, the polarity is inverted as the R61503U draws one frame, which is followed by a blank period lasting for (bp+fp) periods. in case of n-line inversion ac drive, polarity is inverted as the R61503U draws n line, and a blank period lasting for (bp+fp) periods is inserted when the R61503U draws one frame. back porc h alternating timing flame-inversion ac drive back porch front porc h a lternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing alternating timing n-line inversion ac drive front porch n lines n lines n lines n lines n lines n lines n lines n lines n lines frame 1 one-frame period one-frame period n lines figure 64
R61503U specification rev.1.1, march 29, 2007, page 137 of 186 frame-frequency adjustment function the R61503U supports a function to adjust frame frequency. the frame frequency for driving liquid crystal can be adjusted by setting the divi, rtni bits without changing the oscillation frequency. the R61503U allows changing the frame frequency depending on whether moving picture or still picture is displayed on the screen. in this case, set a high oscillation frequency. by changing the divi and rtni settings, the R61503U can operate at high frame frequency when displaying a moving picture, which requires the R61503U to rewrite data in high speed, and it can operate at low frame frequency when displaying a still picture. relationship between liquid crystal drive duty and frame frequency the following equation represent the relationship between liquid crystal drive duty and frame frequency. the frame frequency can be changed by setting the 1h period adjustment bit (rtni) and the operation clock frequency division ratio setting bit (divi). (formula to calculate frame frequency) fosc frame frequency = [hz] clock cycles per line division ratio (line+bp+fp) fosc: rc oscillation frequency line: number of lines to drive a panel (nl bits) clock cycles per line: rtni bits division ratio: divi bits number of lines for front porch: fp number of lines for back porch: bp example of calculation: when maximum frame frequency = 60 hz number of lines to drive a panel: 220 lines 1h period: 16 clock cycles (rtni3-0 = ?0000?) operation clock division ratio: 1/1 front porch (fp): 2 line periods back porch (bp): 14 line periods fosc = 60 (hz) (0+16) (clocks) 1/1 (220 + 16) (lines) = 226 (khz) in this case, the rc oscillation frequency is 226khz. adjust the external resistor connected to the internal rc oscillator to set the frequency to 226khz.
R61503U specification rev.1.1, march 29, 2007, page 138 of 186 partial display function the partial display function allows the R61503U to drive lines selectively to display partial images by setting partial display control registers. the lines not used for displaying partial images are driven at non- lit display level to reduce power consumption. the power efficiency can be enhanced in combination with 8-color display mode. check the display quality when using low power consumption functions. g4 1 g59 non-display area number of lines to drive lcd : nl = 6?h07 (64 lines) base picture display enable : basee = 0 partial image 1 display ram area partial image 1 display position partial image 1 display enable : (ptsa0, ptea0) = (8'h00, 8'h13) : ptdp0 = 8'h28 : ptde0 = 1 non-display area partial image 1 19 lines figure 65 note: see the ?ram address and display position on the panel? for details on the relationship between the display position on the panel and the ram area setting for partial image.
R61503U specification rev.1.1, march 29, 2007, page 139 of 186 low power consumption drive settings the R61503U supports the following low power consumption drive methods to drive the panel with less power requirement. generally, there is a trade-off between power efficiency and quality of display. also, the power efficiency depends on the characteristics of the panel. check which of the following methods can achieve the optimal balance between power consumption and display quality. 1. 8-color display mode (col) in this mode (cl = ?1?), the R61503U halts grayscale voltage generation except for v0 and v31. in this mode, the R61503U display in 8 colors to save power. 2. partial display in this mode, the data is displayed as partial image and the base image is turned off (basee = 0). the normal display operation is limited to the partial display area to save power. the source output level in non-display area can be changed by instruction (pts[2:0]). by setting pts[2:0], it becomes possible to halt the amplifiers for generating grayscale voltage except for v0 and v31 and slow down the clock frequency for step-up operation to half the normal frequency. table 67 source outputs in non-display area source output in non- display area pts[2:0] positive polarity negative polarity non-display area grayscale amp operation non-display area step-up clock frequency 3?h0 v31 v0 v0 to v31 set by dc0, dc1 bits 3?h1 setting disabled setting disabled - - 3?h2 gnd gnd v0 to v31 set by dc0, dc1 bits 3?h3 hi-z hi-z v0 to v31 set by dc0, dc1 bits 3?h4 v31 v0 v0, v31 1/2 the frequency set by dc0, dc1 bits 3?h5 setting disabled setting disabled - - 3?h6 gnd gnd v0, v31 1/2 the frequency set by dc0, dc1 bits 3?h7 hi-z hi-z v0, v31 1/2 the frequency set by dc0, dc1 bits see also ?partial display function? for details.
R61503U specification rev.1.1, march 29, 2007, page 140 of 186 3. frame frequency setting the R61503U allows changing the liquid crystal polarity inversion cycle by changing the frame frequency by setting divi, rtni bits. to improve power efficiency, set a lower frequency in partial display operation, which requires small power consumption. see also ?frame-frequency adjustment function? for details. generally, there is a trade-off between power efficiency and quality of display. the power efficiency also depends on the characteristics of the panel. check the optimal balance between the quality of display on the panel and the power efficiency before use. 4. liquid crystal inversion drive the R61503U allows selecting liquid crystal inversion drive method from frame-inversion ac drive or line-inversion ac drive by setting b/c, nw bits. select the optimal driving method according to the state of display. also, see ?n-line inversion ac drive? for details. generally, there is a trade-off between the power efficiency and the quality of display. the power efficiency also depends on the characteristics of the panel. check the quality of display before use. 5. optimizing step-up factor there are cases that power loss in driving liquid crystal can be minimized by optimizing the step-up factor. whether this method proves to be power-efficient or not depends on the characteristics of the liquid crystal panel. the step-up factor is set by bt[2:0].
R61503U specification rev.1.1, march 29, 2007, page 141 of 186 lcd panel interface timing the following are the relationships between rgb interface signals and lcd panel signals when the display operation is synchronized with the internal clock signal and rgb interface signals respectively. internal clock operation 1 frame period g1 g2 s ( n ) vcom noi 1st line 2nd line 220th line g220 r, g, b sdti r, g, b r, g, b reference point reference point reference point reference point reference point reference point reference point reference point flm figure 66
R61503U specification rev.1.1, march 29, 2007, page 142 of 186 rgb interface signals 1 2 3 4 5 6 220 219 218 1 2 3 bp 1h 5dotcl k see note fp 1 frame vsync hsync dotcl k enable db note: when transferring data via 18-bit rgb interface g1 g2 g3 rgb 220 1 g220 vcom noe 1li ne 2line 3lin e 220line rgb rgb sdte s ( n ) reference point reference point flm figure 67
R61503U specification rev.1.1, march 29, 2007, page 143 of 186 oscillator the R61503U generates rc oscillation using the internal rc oscillator to which an external oscillation resistor is connected between the osc1 and osc2 pins. the oscillation frequency varies depending on the value of external resistor, wiring length, operating power supply voltage. for example, the oscillation frequency can be lowered by connecting an external resistor of a larger resistance, or lowering supply voltage. see ?notes to electrical characteristics? for details on the relationship between rf resistance and oscillation frequency (osc). rf osc1 os c2 rf osc1 os c2 make sure not to arrange other wiring close to or beneath the osc1-osc2 wiring to prevemt coupling. place the rf resistor as close as possible to osc1 and osc2 R61503U R61503U figure 68
R61503U specification rev.1.1, march 29, 2007, page 144 of 186 correction function the R61503U supports -correction function to display in 262,144 colors simultaneously using gradient- adjustment, amplitude-adjustment, fine-adjustment registers. each register consists of positive-polarity register and negative-polarity register to allow different settings for positive and negative polarities and make the optimal gamma correction setting for the characteristics of the panel. r 3 r 2 r 1 g 2 g 1 g 0 b 3 b 2 display da ta msb lsb graphics ram(gram ) r 0 g 3 b 1 b 0 b 4 g 4 g 5 r 4 6 6 6 v1 32 r 5 b 5 32-level grayscale control lcd drive r rg b lcd 8 v0 grayscale amplifie r v3 1 frc contro l 32-level grayscale control lcd driver frc control 32-level grayscale control lcd driver frc contro l pkp 01 pkp 00 pkp 11 pkp 10 pkp 21 pkp 20 pkp 31 pkp 30 pkp 41 pkp 40 pkp 51 pkp 50 pkp 32 pkp 42 pkp 52 pkp 12 pkp 22 pkp 02 positive polarity register prp 01 prp 00 prp 11 prp 10 prp 12 prp 02 vrp 01 vrp 00 vrp 11 vrp 10 vrp 12 vrp 02 vrp 13 vrp 03 vrp 14 vrp 04 negative polarity register pkn 01 pkn 00 pkn 11 pkn 10 pkn 21 pkn 20 pkn 31 pkn 30 pkn 41 pkn 40 pkn 51 pkn 50 pkn 32 pkn 42 pkn 52 pkn 12 pkn 22 pkn 02 prn 01 prn 00 prn 11 prn 10 prn 12 prn 02 vrn 01 vrn 00 vrn 11 vrn 10 vrn 12 vrn 02 vrn 13 vrn 03 vrn 14 vrn 04 figure 69
R61503U specification rev.1.1, march 29, 2007, page 145 of 186 grayscale amplifier unit in grayscale amplifier unit, 8 levels vin0 ~ vin7 are determined by gradient and fine adjustment registers. then, the 8 levels are divided by the internal ladder resistors between grayscale amplifiers and 32 grayscale levels (v0 ~ v31) are generated. increment adjustment fine adjustment(6 x 3 bits) amplitude adjustment 8 to 1 select or 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 select or ladder resi stor unit grayscale amplifier unit prp/n0,prp/n1 vrp/n0 3 3 3 3 3 3 3 3 5 pkp/n0 pkp/n1 pkp/n2 pkp/n3 pkp/n4 pkp/n5 vinp0 /vin n0 vinp1 /vinn1 vinp2 /vinn2 vinp3 /vinn3 vinp4 /vinn4 vinp5 /vinn5 vinp6 /vinn6 vinp7 /vin n7 v0 v1 v2 v3 v8 v9 v16 v17 v19 v20 v24 v25 v30 v31 v26 vreg1ou t vgs vrp/n1 5 figure 70
R61503U specification rev.1.1, march 29, 2007, page 146 of 186 8 to 1 se l l rp1 rp2 rp3 rp4 rp5 rp6 rp7 kvp0 kvp1 kvp2 kvp3 kvp4 kvp5 kvp6 kvp7 kvp8 rp0 vr hp rp9 rp10 kv p9 rp1 1 rp1 2 rp1 3 rp1 4 rp 8 kvp10 kvp11 kvp12 kvp13 kvp14 kvp15 kvp1 6 rp15 kvp1 7 kvp18 kvp19 kvp20 kvp21 kvp22 kvp23 kvp24 rp1 6 rp1 7 rp1 8 rp1 9 rp2 0 rp2 1 rp2 2 rp23 kvp2 5 kvp26 kvp27 kvp28 kvp29 kvp30 kvp31 kvp32 rp2 4 rp2 5 rp2 6 rp2 7 rp2 8 rp2 9 rp3 0 rp31 kvp3 3 kvp34 kvp35 kvp36 kvp37 kvp38 kvp39 kvp40 rp3 2 rp3 3 rp3 4 rp3 5 rp3 6 rp3 7 rp3 8 vrlp kvp4 1 kvp42 kvp43 kvp44 kvp45 kvp46 kvp47 kvp4 8 rp39 rp40 rp41 rp42 rp43 rp44 rp4 5 kvp49 rp46 vr p1 rp47 vi inp 2 pr p0[2:0] pk p1[2:0] vi inp 1 pk p0[2:0] vi inp 0 vi inp 3 pkp2[2:0] vi inp 4 pkp3[2:0] vi inp 5 pkp4[2:0] vi inp 6 pk p5[2:0] vi inp 7 pr p1[2:0] vrp 1[4:0] rn1 rn2 rn3 rn4 rn5 rn6 rn7 kvn1 kvn2 kvn3 kvn4 kvn5 kvn6 kvn7 kvn8 rn0 vr hn rn9 rn10 kv n9 rn1 1 rn1 2 rn1 3 rn1 4 rn 8kvn10 kvn11 kvn12 kvn13 kvn14 kvn15 kvn1 6 rn15 kvn1 7 kvn18 kvn19 kvn20 kvn21 kvn22 kvn23 kvn24 rn1 6 rn1 7 rn1 8 rn1 9 rn2 0 rn2 1 rn2 2 rn23 kvn2 5 kvn26 kvn27 kvn28 kvn29 kvn30 kvn31 kvn32 rn2 4 rn2 5 rn2 6 rn2 7 rn2 8 rn2 9 rn3 0 rn31 kvn3 3 kvn34 kvn35 kvn36 kvn37 kvn38 kvn39 kvn40 rn3 2 rn3 3 rn3 4 rn3 5 rn3 6 rn3 7 rn3 8 vrln kvn4 1 kvn42 kvn43 kvn44 kvn45 kvn46 kvn47 kvn4 8 rn39 rn40 rn41 rn42 rn43 rn44 rn4 5 kvn49 rn46 vr n rn47 vinn2 prn 0[2:0] pkn 1[2:0] vinn1 pk n0[2:0] vinn3 pkn 2[2:0] vinn4 pk n3[2:0] vinn5 pkn 4[2:0] vinn6 pkn 5[2:0] vinn7 prn 1[2:0] vrn 1[4:0] vreg1out 5r 4r 1r 1r 1r 1r 4r 5r 16r 5r 5r 8r 0 ~28r 0~28r 0~31r 5r 4r 1r 1r 4r 5r 16r 5r 8r 0 ~28r 0 ~28r 0~ 31r vgs vr p0[4:0] vrp0 0 ~3 1r kvn0 vinn0 vrn 0[4:0] vrn0 0 ~31r 1r 5r 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 8 to 1 se l l 1r figure 71 reference voltage generating block (ladder resistor units and 8-to-1 selectors)
R61503U specification rev.1.1, march 29, 2007, page 147 of 186 correction registers the -correction registers of the R61503U consists of gradient-adjustment, amplitude-adjustment, fine- adjustment registers to correct grayscale voltage levels according to the gamma characteristics of the liquid crystal panel. these register settings make adjustments to the relationship between the grayscale number and its corresponding grayscale voltage level and the setting can be made differently for positive and negative polarities (the reference level and the register settings are the same for all rgb dots). the function of each register is as follows. grayscale voltage grayscale number (vx) gradient adjustment grayscale voltage fine adjustment grayscale voltage amplitude adjustment grayscale number (vx) grayscale number (vx) figure 72 1. gradient adjustment registers the gradient adjustment registers are used to adjust the gradients in the middle grayscale range without changing the dynamic range. adjustments are made by changing the resistance values of the resistors (vrhp(n)/vrlp(n)) in the middle of the ladder resistor unit. the gradient adjustment registers consist of positive and negative polarity registers to allow asymmetric drive. 2. amplitude adjustment registers the amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage by changing the resistance values of the resistors (vrp(n)1/0) at both ends of the ladder resistor unit. same with the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. 3. fine adjustment registers the fine adjustment registers are used for minute adjustment of grayscale voltage. the fine adjustment register represent one voltage level to be selected in the 8-to-1 selector among 8 levels generated from the ladder resistor unit. same with other registers, the fine adjustment registers consist of positive and negative polarity registers.
R61503U specification rev.1.1, march 29, 2007, page 148 of 186 table 68 correction register register positive negative function prp0[2:0] prn0[2:0] variable resistor vrhp(n) gradient prp1[2:0] prn1[2:0] variable resistor vrlp(n) vrp0[4:0] vrn0[4:0] variable resistor vrp(n)0 amplitude vrp1[4:0] vrn1[4:0] variable resistor vrp(n)1 pkp0[2:0] pkn0[2:0] 8 to1 selector (grayscales1-3 voltage levels) pkp1[2:0] pkn1[2:0] 8 to1 selector (grayscale 4 voltage level) pkp2[2:0] pkn2[2:0] 8 to1 selector (grayscale 10 voltage level) pkp3[2:0] pkn3[2:0] 8 to1 selector (grayscale 21 voltage level) pkp4[2:0] pkn4[2:0] 8 to1 selector (grayscale 27 voltage level) fine adjustment pkp5[2:0] pkn5[2:0] 8 to1 selector (grayscale 28-30 voltage levels) reference voltage generating block (ladder resistor units and 8-to-1 selectors) block configuration the ladder resistor and 8-to-1 selector unit shown in page 144 consists of two ladder resistor unit including variable resistors and 8-to-1 selectors which selects a voltage generated by the ladder resistor unit and output the reference voltage from which grayscale voltages are generated. the correction registers represent the resistance values of these resistors in the ladder resistor unit and the reference levels selected in the 8-to-1 selectors (see table 68 correction register). variable resistors the R61503U uses variable resistors for the following three purposes: gradient adjustment (vrhp(n)/vrlp(n)); amplitude adjustment (1) (vrp(n)0); and amplitude adjustment (2) (vrp(n)1). the resistance values are determined by gradient adjustment and amplitude adjustment registers as below. table 69 table 70 table 71 gradient adjustment amplitude adjustment (1) amplitude adjustment (2) register prp(n) 0/1[2:0] resistance vrhp(n) vrlp(n) register vrp(n)0[4:0] resistance vrp(n)0 register vrp(n)1[4:0] resistance vrp(n)1 000 0r 00000 0r 00000 0r 001 4r 00001 1r 00001 1r 010 8r 00010 2r 00010 2r 011 12r : : : : 100 16r : : : : 101 20r 11101 29r 11101 29r 110 24r 11110 30r 11110 30r 111 28r 11111 31r 11111 31r
R61503U specification rev.1.1, march 29, 2007, page 149 of 186 8-to-1 selector the 8-to-1 selector selects one voltage level according to the fine adjustment register setting among the voltages generated by ladder resistors, and outputs the selected level as one of the reference voltages (vinp(n)1~6). the following table shows the correspondence between the selected voltage levels and the fine-adjustment register settings for respective reference voltage levels (vinp(n)1~6). table 72 fine adjustment registers and selected voltage register bits selected voltage leve l (reference grayscale voltage level) pkp(n)0/1[2:0] vinp(n)1 vinp(n)2 vinp(n)3 vinp(n)4 vinp(n)5 vinp(n)6 000 kvp(n)1 kvp(n)9 kvp(n) 17 kvp(n)25 kvp(n)33 kvp(n)41 001 kvp(n)2 kvp(n)10 kvp(n) 18 kvp(n)26 kvp(n)34 kvp(n)42 010 kvp(n)3 kvp(n)11 kvp(n) 19 kvp(n)27 kvp(n)35 kvp(n)43 011 kvp(n)4 kvp(n)12 kvp(n) 20 kvp(n)28 kvp(n)36 kvp(n)44 100 kvp(n)5 kvp(n)13 kvp(n) 21 kvp(n)29 kvp(n)37 kvp(n)45 101 kvp(n)6 kvp(n)14 kvp(n) 22 kvp(n)30 kvp(n)38 kvp(n)46 110 kvp(n)7 kvp(n)15 kvp(n) 23 kvp(n)31 kvp(n)39 kvp(n)47 111 kvp(n)8 kvp(n)16 kvp(n) 24 kvp(n)32 kvp(n)40 kvp(n)48
R61503U specification rev.1.1, march 29, 2007, page 150 of 186 the grayscale levels v1 ~ v 31 is calculated from the following formula. table 73 grayscale voltage calculation formula (positive polarity) pin formula fine-adjustment register reference voltage kvp0 vreg1out- v*vrp0/sumrp vinp0 kvp1 vreg1out- v*(vrp0+5r)/sumrp pkp02-00=?000? kvp2 vreg1out- v*(vrp0+9r)/sumrp pkp02-00=?001? kvp3 vreg1out- v*(vrp0+13r)/sumrp pkp02-00=?010? kvp4 vreg1out- v*(vrp0+17r)/sumrp pkp02-00=?011? kvp5 vreg1out- v*(vrp0+21r)/sumrp pkp02-00=?100? kvp6 vreg1out- v*(vrp0+25r)/sumrp pkp02-00=?101? kvp7 vreg1out- v*(vrp0+29r)/sumrp pkp02-00=?110? kvp8 vreg1out- v*(vrp0+33r)/sumrp pkp02-00=?111? vinp1 kvp9 vreg1out- v* vrp0+33r+vrhp /sumrp pkp12-10=?000? kvp10 vreg1out- v* vrp0+34r+vrhp /sumrp pkp12-10=?001? kvp11 vreg1out- v* vrp0+35r+vrhp /sumrp pkp12-10=?010? kvp12 vreg1out- v* vrp0+36r+vrhp /sumrp pkp12-10=?011? kvp13 vreg1out- v* vrp0+37r+vrhp /sumrp pkp12-10=?100? kvp14 vreg1out- v* vrp0+38r+vrhp /sumrp pkp12-10=?101? kvp15 vreg1out- v* vrp0+39r+vrhp /sumrp pkp12-10=?110? kvp16 vreg1out- v* vrp0+40r+vrhp /sumrp pkp12-10=?111? vinp2 kvp17 vreg1out- v* vrp0+45r+vrhp /sumrp pkp22-20=?000? kvp18 vreg1out- v* vrp0+46r+vrhp /sumrp pkp22-20=?001? kvp19 vreg1out- v* vrp0+47r+vrhp /sumrp pkp22-20=?010? kvp20 vreg1out- v* vrp0+48r+vrhp /sumrp pkp22-20=?011? kvp21 vreg1out- v* vrp0+49r+vrhp /sumrp pkp22-20=?100? kvp22 vreg1out- v* vrp0+50r+vrhp /sumrp pkp22-20=?101? kvp23 vreg1out- v* vrp0+51r+vrhp /sumrp pkp22-20=?110? kvp24 vreg1out- v* vrp0+52r+vrhp /sumrp pkp22-20=?111? vinp3 kvp25 vreg1out- v* vrp0+68r+vrhp /sumrp pkp32-30=?000? kvp26 vreg1out- v* vrp0+69r+vrhp /sumrp pkp32-30=?001? kvp27 vreg1out- v* vrp0+70r+vrhp /sumrp pkp32-30=?010? kvp28 vreg1out- v* vrp0+71r+vrhp /sumrp pkp32-30=?011? kvp29 vreg1out- v* vrp0+72r+vrhp /sumrp pkp32-30=?100? kvp30 vreg1out- v* vrp0+73r+vrhp /sumrp pkp32-30=?101? kvp31 vreg1out- v* vrp0+74r+vrhp /sumrp pkp32-30=?110? kvp32 vreg1out- v* vrp0+75r+vrhp /sumrp pkp32-30=?111? vinp4 kvp33 vreg1out- v* vrp0+80r+vrhp /sumrp pkp42-40=?000? kvp34 vreg1out- v* vrp0+81r+vrhp /sumrp pkp42-40=?001? kvp35 vreg1out- v* vrp0+82r+vrhp /sumrp pkp42-40=?010? kvp36 vreg1out- v* vrp0+83r+vrhp /sumrp pkp42-40=?011? kvp37 vreg1out- v* vrp0+84r+vrhp /sumrp pkp42-40=?100? kvp38 vreg1out- v* vrp0+85r+vrhp /sumrp pkp42-40=?101? kvp39 vreg1out- v* vrp0+86r+vrhp /sumrp pkp42-40=?110? kvp40 vreg1out- v* vrp0+87r+vrhp /sumrp pkp42-40=?111? vinp5 kvp41 vreg1out- v* vrp0+87r+vrhp+vrlp /sumrp pkp52-50=?000? kvp42 vreg1out- v* vrp0+91r+vrhp+vrlp /sumrp pkp52-50=?001? kvp43 vreg1out- v* vrp0+95r+vrhp+vrlp /sumrp pkp52-50=?010? kvp44 vreg1out- v* vrp0+99r+vrhp+vrlp /sumrp pkp52-50=?011? kvp45 vreg1out- v* vrp0+103r+vrhp+vrlp /sumrp pkp52-50=?100? kvp46 vreg1out- v* vrp0+107r+vrhp+vrlp /sumrp pkp52-50=?101? kvp47 vreg1out- v* vrp0+111r+vrhp+vrlp /sumrp pkp52-50=?110? kvp48 vreg1out- v* vrp0+115r+vrhp+vrlp /sumrp pkp52-50=?111? vinp6 kvp49 vreg1out- v* vrp0+120r+vrhp+vrlp /sumrp vinp7 sumrp : sum of positive polarity ladder resistors = 128r+vrhp+vrlp+vrp0+vrp1 v : electrical potential between vreg1out and vgs
R61503U specification rev.1.1, march 29, 2007, page 151 of 186 table 74 grayscale voltage calculation formula (positive polarity) grayscale formula v0 vinp0 v1 v4+(vinp1-v4)*(15/24) v2 v4+(vinp1-v4)*(8/24) v3 v4+(vinp1-v4)*(4/24) v4 vinp2 v5 v10+(v4-v10)*(20/24) v6 v10+(v4-v10)*(16/24) v7 v10+(v4-v10)*(12/24) v8 v10+(v4-v10)*(8/24) v9 v10+(v4-v10)*(4/24) v10 vinp3 v11 v21+(v10-v21)*(21/24) v12 v21+(v10-v21)*(19/24) v13 v21+(v10-v21)*(17/24) v14 v21+(v10-v21)*(15/24) v15 v21+(v10-v21)*(13/24) v16 v21+(v10-v21)*(11/24) v17 v21+(v10-v21)*(9/24) v18 v21+(v10-v21)*(7/24) v19 v21+(v10-v21)*(5/24) v20 v21+(v10-v21)*(3/24) v21 vinp4 v22 v27+(v21-v27)*(20/24) v23 v27+(v21-v27)*(16/24) v24 v27+(v21-v27)*(12/24) v25 v27+(v21-v27)*(8/24) v26 v27+(v21-v27)*(4/24) v27 vinp5 v28 vinp6+(v27-vinp6)*(20/24) v29 vinp6+(v27-vinp6)*(16/24) v30 vinp6+(v27-vinp6)*(9/24) v31 vinp7 make sure ddvdh ? v0 > 0.5v and ddvdh ? v8 >1.1v.
R61503U specification rev.1.1, march 29, 2007, page 152 of 186 table 75 grayscale voltage calculation formula (negative polarity) pin formula fine-adjustment register reference voltage kvn0 vreg1out- v*vrn0/sumrn vinn0 kvn1 vreg1out- v*(vrn0+5r)/sumrn pkn02-00=?000? kvn2 vreg1out- v*(vrn0+9r)/sumrn pkn02-00=?001? kvn3 vreg1out- v*(vrn0+13r)/sumrn pkn02-00=?010? kvn4 vreg1out- v*(vrn0+17r)/sumrn pkn02-00=?011? kvn5 vreg1out- v*(vrn0+21r)/sumrn pkn02-00=?100? kvn6 vreg1out- v*(vrn0+25r)/sumrn pkn02-00=?101? kvn7 vreg1out- v*(vrn0+29r)/sumrn pkn02-00=?110? kvn8 vreg1out- v*(vrn0+33r)/sumrn pkn02-00=?111? vinn1 kvn9 vreg1out- v* vrn0+33r+vrhn /sumrn pkn12-10=?000? kvn10 vreg1out- v* vrn0+34r+vrhn /sumrn pkn12-10=?001? kvn11 vreg1out- v* vrn0+35r+vrhn /sumrn pkn12-10=?010? kvn12 vreg1out- v* vrn0+36r+vrhn /sumrn pkn12-10=?011? kvn13 vreg1out- v* vrn0+37r+vrhn /sumrn pkn12-10=?100? kvn14 vreg1out- v* vrn0+38r+vrhn /sumrn pkn12-10=?101? kvn15 vreg1out- v* vrn0+39r+vrhn /sumrn pkn12-10=?110? kvn16 vreg1out- v* vrn0+40r+vrhn /sumrn pkn12-10=?111? vinn2 kvn17 vreg1out- v* vrn0+45r+vrhn /sumrn pkn22-20=?000? kvn18 vreg1out- v* vrn0+46r+vrhn /sumrn pkn22-20=?001? kvn19 vreg1out- v* vrn0+47r+vrhn /sumrn pkn22-20=?010? kvn20 vreg1out- v* vrn0+48r+vrhn /sumrn pkn22-20=?011? kvn21 vreg1out- v* vrn0+49r+vrhn /sumrn pkn22-20=?100? kvn22 vreg1out- v* vrn0+50r+vrhn /sumrn pkn22-20=?101? kvn23 vreg1out- v* vrn0+51r+vrhn /sumrn pkn22-20=?110? kvn24 vreg1out- v* vrn0+52r+vrhn /sumrn pkn22-20=?111? vinn3 kvn25 vreg1out- v* vrn0+68r+vrhn /sumrn pkn32-30=?000? kvn26 vreg1out- v* vrn0+69r+vrhn /sumrn pkn32-30=?001? kvn27 vreg1out- v* vrn0+70r+vrhn /sumrn pkn32-30=?010? kvn28 vreg1out- v* vrn0+71r+vrhn /sumrn pkn32-30=?011? kvn29 vreg1out- v* vrn0+72r+vrhn /sumrn pkn32-30=?100? kvn30 vreg1out- v* vrn0+73r+vrhn /sumrn pkn32-30=?101? kvn31 vreg1out- v* vrn0+74r+vrhn /sumrn pkn32-30=?110? kvn32 vreg1out- v* vrn0+75r+vrhn /sumrn pkn32-30=?111? vinn4 kvn33 vreg1out- v* vrn0+80r+vrhn /sumrn pkn42-40=?000? kvn34 vreg1out- v* vrn0+81r+vrhn /sumrn pkn42-40=?001? kvn35 vreg1out- v* vrn0+82r+vrhn /sumrn pkn42-40=?010? kvn36 vreg1out- v* vrn0+83r+vrhn /sumrn pkn42-40=?011? kvn37 vreg1out- v* vrn0+84r+vrhn /sumrn pkn42-40=?100? kvn38 vreg1out- v* vrn0+85r+vrhn /sumrn pkn42-40=?101? kvn39 vreg1out- v* vrn0+86r+vrhn /sumrn pkn42-40=?110? kvn40 vreg1out- v* vrn0+87r+vrhn /sumrn pkn42-40=?111? vinn5 kvn41 vreg1out- v* vrn0+87r+vrhn+vrln /sumrn pkn52-50=?000? kvn42 vreg1out- v* vrn0+91r+vrhn+vrln /sumrn pkn52-50=?001? kvn43 vreg1out- v* vrn0+95r+vrhn+vrln /sumrn pkn52-50=?010? kvn44 vreg1out- v* vrn0+99r+vrhn+vrln /sumrn pkn52-50=?011? kvn45 vreg1out- v* vrn0+103r+vrhn+vrln /sumrn pkn52-50=?100? kvn46 vreg1out- v* vrn0+107r+vrhn+vrln /sumrn pkn52-50=?101? kvn47 vreg1out- v* vrn0+111r+vrhn+vrln /sumrn pkn52-50=?110? kvn48 vreg1out- v* vrn0+115r+vrhn+vrln /sumrn pkn52-50=?111? vinn6 kvn49 vreg1out- v* vrn0+120r+vrhn+vrln /sumrn vinn7 sumrn : sum of negative polarity ladder resistors = 128r+vrhn+vrln+vrn0+vrn1 v : electrical potential between vreg1out and vgs
R61503U specification rev.1.1, march 29, 2007, page 153 of 186 table 76 grayscale voltage calculation formula (negative polarity) grayscale formula v0 vinn0 v1 v4+(vinn1-v4)*(15/24) v2 v4+(vinn1-v4)*(8/24) v3 v4+(vinn1-v4)*(4/24) v4 vinn2 v5 v10+(v4-v10)*(20/24) v6 v10+(v4-v10)*(16/24) v7 v10+(v4-v10)*(12/24) v8 v10+(v4-v10)*(8/24) v9 v10+(v4-v10)*(4/24) v10 vinn3 v11 v21+(v10-v21)*(21/24) v12 v21+(v10-v21)*(19/24) v13 v21+(v10-v21)*(17/24) v14 v21+(v10-v21)*(15/24) v15 v21+(v10-v21)*(13/24) v16 v21+(v10-v21)*(11/24) v17 v21+(v10-v21)*(9/24) v18 v21+(v10-v21)*(7/24) v19 v21+(v10-v21)*(5/24) v20 v21+(v10-v21)*(3/24) v21 vinn4 v22 v27+(v21-v27)*(20/24) v23 v27+(v21-v27)*(16/24) v24 v27+(v21-v27)*(12/24) v25 v27+(v21-v27)*(8/24) v26 v27+(v21-v27)*(4/24) v27 vinn5 v28 vinn6+(v27-vinn6)*(20/24) v29 vinn6+(v27-vinn6)*(16/24) v30 vinn6+(v27-vinn6)*(9/24) v31 vinn7 make sure ddvdh ? v0 > 0.5v and ddvdh ? v8 >1.1v.
R61503U specification rev.1.1, march 29, 2007, page 154 of 186 ram data (rgb dot data bits) and the source output level negative polarity positive polarity output level v31 v0 000000 111111 ram data note: the source output and ram data relationship is the same for all rgb dot figure 73 positive polarity negative polarity sn vcom figure 74 source output waveform and vcom polarity
R61503U specification rev.1.1, march 29, 2007, page 155 of 186 power supply generating circuit the following is the configuration of lcd drive voltage generating circuit of the R61503U. power supply circuit connection example1 (vci1=vciout) the vciout output circuit changes the vciout level in this example. grayscale voltage generating circuit vgl ddv dh c13- c13+ c21- c21+ c22- c22+ c11- c11+ vciout vcom output circuit vcomr vcomh vcoml vcom vci1 vgh source driver s1-s528 vcom level adjustment circuit R61503U vcilvl vr eg1out see note 1 vdd step-up circuit 2 g1-g220 vgh gate driver vgl vcc gnd/rgnd vci a gnd vcilvl step-up circuit 1 output circuit internal reference voltage generating circuit vcl iovcc (15) (14) (13) (4) (3) (2) (1) (12) (11) (10) (9) (8) (7) (6) (5) vreg1 regulator notes: 1. the wiring resist ances between gnd/vgl to the schottky diodes must be 10 or less. 2. when directly applying vci to vci1, set vc = 3?h7. capacitor connection is not required for vciout output. figure 75
R61503U specification rev.1.1, march 29, 2007, page 156 of 186 specifications of external elemen ts for the power supply circuit the specifications of external elements connected to the power supply circuit of the R61503U are as follows. table 77 capacitor capacitance upper voltage limit pin connection 6v (2) vci1, (3) c11+/- (5) c13+/-, (12) vcl, (14) vcoml 10v (4) ddvdh, (13) vcomh 1f characteristics b 25v (10) vgl 10v (6) c21+/-, (7) c22+/- 0.47f characteristics b 25v (9) vgh 0.1f characteristics b 10v (1) vreg1out notes: 1. check the capacitor by connecting it on the lc module. 2. the numbers in the parentheses correspond to the numbers in figure 74. table 78 schottky diode specification pin connection vf 0.4v/20ma@25 , vr R 25v (recommended diode: hsc226) (8) ddvdh-vgh (11) gnd-vgl table 79 variable resistor specification pin connection 200k (2) vcomr table 80 internal logic power supply capacitor recommended voltage proof pin connection 1 f (b characteristics) 6v (15) vdd table 81 oscillator resistance condition of usage pin connection rf rf 1mw 1% osc1-osc2
R61503U specification rev.1.1, march 29, 2007, page 157 of 186 voltage generation diagram the following are the diagrams of voltage generation in the R61503U and the tft display application voltage waveforms and electrical potential relationship. vcilvl(2.5 ~ 3.3v) gnd(0v) vcc (2.5 ~ 3.6v) vc vci1 vreg1out vrh3-0 vreg1out(3.5v ~ (ddvdh-0.5)v) ddvdh (4.5v ~ 6.0v) bt bt vcoml ((vcl+0.5) ~ gnd) bt ddvdh vgh vgl iovcc(1.65 ~ 3.6v) vcm4-0 vcomh (2.5v ~ (ddvdh-0.5)v) vdv3-0 vcl (gnd ~ 3.3v) vcl vcomg vci (2.5 ~ 3.3v) vgh-vgl amplitude 28.0v (max.) figure 76 pattern diagram for voltage setting notes: 1. the ddvdh, vgh, vgl output voltages will become lower than their theoretical levels (ideal voltages) due to current consumption at respective outputs. make sure that output voltage levels in operation do not conflict with the following conditions: (ddvdh ? vreg1out) > 0.5v, (ddvdh ? vcomh) > 0.5v, (vcoml ? vcl) > 0.5v. when the alternating cycle of vcom is high (e.g. polarity inverts every line cycle), current consumption will increase. in this case, check the voltage before use. 2. the operating voltage ranges must be determined with due care so that the absolute maximum ratings are maintained.
R61503U specification rev.1.1, march 29, 2007, page 158 of 186 gn (panel interface output) vgh vcomh vgl vreg1out sn(source driver output) vc om vcoml figure 77 tft display application voltage waveform and electrical potential
R61503U specification rev.1.1, march 29, 2007, page 159 of 186 power supply setting sequence the following are the sequences for setting power supply on/off instructions. set power supply on/off instructions according to the following sequences in display on/off, sleep set/exit sequences. power supply (vcc, vci, iovcc) on power on sequence power supply off sequence normal display display off sequence power supply halt setting r10h: ap = 2'h 0, sap=0 r11h: dc0 = 3'h6 r12h: pon = 0 r13h vcomg = 0 dte=1, d=2'h3, gon=1, von=1, vcomg =1 vcc iovcc vci vcc :w>":w iovcc :w>" vci or vcc, iovcc, vci simultaneously gnd vci vci :w>":w iovcc :w>" vcc gnd iovcc vcc r10h: ape=0 1 frame or more power on reset 2ms or more powr supply off setting dte = 0, d=2'h0, gon=0 pon = 0, von = 0 r07h: d=2'h1 initial instruction setting user setting (1) nl, bp, fp, gamma settings and others rs=0, db=16'h0000 rs=0, db=16'h0000 rs=0, db=16'h0000 rs=0, db=16'h0000 r10h: ape = 1, ap, bt, sap=1 r11h: vc, dc0, dc1 r12h: vrh, pon=1, vcmr = 1, von=0 r13h: vcm, vdv, vcomg = 1 display on sequence other mode setting instruction lcd power supply on sequence r18h: pse=1'h1 r12h: pson=1'h1 transfer synchronization power supply user setting power supply startup time (8 frames x 1/osc) power supply halt setting or vcc, iovcc, vci simultaneously power supply (vcc, vci, iovcc) off lcd power supply off sequence ra4h: calb = 1 1/fosc x 8 wait figure 78
R61503U specification rev.1.1, march 29, 2007, page 160 of 186 instruction setting the following are the sequences for various instruction settings. when setting instruction in the R61503U, follow the sequence below. display on/off r07h: gon=0, dte=0, d=2'h0 lcd power supply off sequence* see note display off display on lcd power supply on sequence* see note display off sequence display on sequence display off 2 frame periods or more r07h: gon=0, dte= 0, d=2'h1 display on note: see power supply setting sequences 8h periods or more r07h: gon=1, dte= 0, d=2'h1 display on (1) r07h: besee=1, gon=1, dte= 1, d=2'h3 display on (3) r07h: gon=0, dte=0, d=2'h2 r12h: von =0 display off 2 frame periods or more 8h periods or more r12h: vrh, pon = 1, vcmr, von=1 display on (2) figure 79
R61503U specification rev.1.1, march 29, 2007, page 161 of 186 sleep/standby mode display on sequence* see note display off sequence* see note sleep mode sequence 1clock or more r10h: slp=0 sleep exit r10h: slp=1 sleep set set sleep mode exit sleep mode standby mode note: see display on/off setting sequences. display on sequence* see note display off sequence* see note 1ms or more start oscillation r10h: stb=1 standby set set standby mode exit standby mode r10h: stb=0 standby exit figure 80
R61503U specification rev.1.1, march 29, 2007, page 162 of 186 deep standby mode r100h: dstb = 1 cs = low (1) vdd startup, oscillator stabilizing period set deep standby mode set deep standby mode 1 ms or more initialize the R61503U exit deep standby mode input cs = low 6 times deep standby mode cs = low (2) cs = low (3) cs = low (4) cs = low (5) cs = low (6) display off sequence* see note 1 exit deep standby mode by input of cs = "low" 18-/16-/9-/8-bit interface notes: 1. see ac characteristics in "electrical characteristics" for details on low width (pwlw), high width (pwhw), and cycle (tcycw) periods. 2. leave at least 1 ms between the 2nd and 3rd inputs of cs = low. initial instruction setting display on sequence cs wr rd rs data "high" "high" "low" or "high" don't care don't care don't care don't care don't care don't care 1 2 3 4 5 6 data and rs = don't care. waveforms in exiting deep standby mode (cs = "low") ram data setting ra4h: calb = 1 wait 1/fosc x 8 wait 1ms or more figure 81
R61503U specification rev.1.1, march 29, 2007, page 163 of 186 exit deep standby mode by index write of cs = "low" and of wr = "low". (1) 18-/16-bit interface operation display off sequence set deep standby mode r100h: dstb = 1 index write (data = 16'h0000) index write (data = 16'h0000) index write (data = 16'h0000) index write (data = 16'h0000) index write (data = 16'h0000) index write (data = 16'h0000) vdd startup oscillator stabilizing period initialize the R61503U exit deep standby mode 1ms or more set deep standby mode initial instruction setting display on sequence notes: 1. see ac characteristics in "electrical characteristics" for details on low width (pwlw), high width (pwhw), and cycle (tcycw) periods. 2. leave at least 1 ms between the 2nd and 3rd inputs of index write. cs wr rd rs data 16'h0000 "high" "low" 1 2 3 4 5 6 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 waveforms in exiting deep standby mode (rs = "low", index write) ram data setting wait 1/fosc x 8 wait 1ms or more ra4h: calb = 1 figure 82
R61503U specification rev.1.1, march 29, 2007, page 164 of 186 index write ( data=8?h00 ) index write ( data=8?h00 ) index write ( data=8?h00 ) index write ( data=8?h00 ) index write ( data=8?h00 ) index write ( data=8?hff ) index write ( data=8?h00 ) index write ( data=8?h00 ) index write ( data=8?h00 ) index write ( data=8?h00 ) (2) 9-/8-bit interface operation vdd startup oscillation stabilizing period 1ms or more transfer synchronization command initialize the R61503U exit deep standby mode display off sequence r100h: dstb = 1 set deep standby mode set deep standby mode ram data setting display on sequence cs wr rd rs data transfer synchronization 00h 00h 00h 00h ffh 00h 00h 00h 00h 00h upper iw upper iw upper iw upper iw upper iw lower iw lower iw lower iw lower iw lower iw 4 3 2 1 1 2 3 4 5 6 execute transfer synchronization command after exiting deep standby mode by input of rs = low and index write. notes: 1. see ac characteristics in "electrical characteristics" for details on low width (pwlw), high width (pwhw), and cycle (tcycw) periods. 2. leave at least 1 ms between the 2nd and 3rd inputs of index write. 3. set transfer synchronization command dara to 8'h00 in 8-bit interface operation, and 9'h00 in 9-bit interface operation, respectively. waveforms in exiting deep standby mode (rs = "low", index write) initial instruction setting wait 1/fosc x 8 ra4h: calb = 1 wait 1ms or more figure 83
R61503U specification rev.1.1, march 29, 2007, page 165 of 186 nv memory control the R61503U incorporates 8-bits x 3 address nv memory. user identification code is written in the nv memory address 0?h. vcomh setting instruction is written in the nv memory addresses 1?h, 2?h. the R61503U?s nv memory has two addresses for vcomh setting to allow changing the vcomh setting. when writing the vcomh setting for the first time, write the setting in the address 1?h. write the setting in the address 2?h when writing the setting for the second time. make sure to write ?1? to evcm0 and evcm1 bits. when the second vcomh setting is written in the address 2?h, the second setting is enabled. the vcmsel bit in the r13h register determines whether the setting in the nv memory or the vcm[4:0] setting (externally inputted instruction) is enabled to set the vcomh level. set vcmsel = 1, when enabling the nv memory setting. set vcmsel = 0, when not using the nv memory setting. when writing the setting to the nv memory, make sure to follow the nv memory write sequence. by performing an nv memory read operation, the setting written in nv memory is read out. in this case, follow the nv memory read sequence. in case of setting calb = 1 (ra4h: calibration to internal operation) after power-on reset, the data written in the nv memory is stored in the nv memory read register.
R61503U specification rev.1.1, march 29, 2007, page 166 of 186 data write index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a0h 0 0 0 0 0 0 0 0 te 0 eop1 eop0 0 0 ead1 ead0 a0h 0 0 0 0 0 0 0 0 ed7 ed6 e d5 ed4 ed3 ed2 ed1 ed0 00 0 0 0 0 uid3 uid2 uid1 uid0 01 evcm 0 0 evcm evcm evcm evcm evcm 0 04 03 02 01 00 02 evcm 0 0 evcm evcm evcm evcm evcm 1 14 13 12 11 10 ead1/0 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 28'h 0 0 0 0 0 0 0 0 0 0 0 0 uid3 uid2 uid1 uid0 29'h 0 0 0 0 0 0 0 0 evcm 0 0 evcm evcm evcm evcm evcm 0 04 03 02 01 00 2a'h 0 0 0 0 0 0 0 0 evcm 0 0 evcm evcm evcm evcm evcm 1 14 13 12 11 10 index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13'h 0 0 0 0 vdv vdv vdv vdv vcm 0 0 vcm vcm vcm vcm vcm 03 02 01 00 sel 04 03 02 01 00 data read out/calb = 1 vcomh level internal electronic volume selector evcm1/0 01 enable evcm0[4:0] setting (r29'h) 11 enable evcm1[4:0] setting (r2a'h) vcmsel 0 enable vcm[4:0] setting (r13'h) 1 enable evcm0[4:0] or evcm1[4:0] (r29'h or r2a'h) make sure to write "1" to evcm0/evcm1 ead1/0 nv memory write address ed[7:0] nv memory data write control register 00 user id code vcomh level setting 1 vcomh level setting 2 nv memory write data 01 10 nv memory write control te 0 1 00 01 10 data write rewrite data halt nv memory control bit eop1/0 data write end data write start power control 4 register nv memory data read register figure 84 nv memory system configuration
R61503U specification rev.1.1, march 29, 2007, page 167 of 186 nv memory write/read sequences vpp1 vpp2 vpp3 gnd vcc iovcc1 , 2 vci gnd rs=0, db=16h0000 rs=0, db=16h0000 rs=0, db=16h0000 rs = 0, db = 16 h0000 ra1:16h00** ra0:16h0090 (te=1,eop=2h1,ead=2h0) ra0:16h0000 (te=0,eop=2h0,ead=2h0) gnd vpp1 = 9.0 0.3v vpp2 = 7.5 0.3v gnd vpp1 = 9.0 0.3v vpp2 = 7.5 0.3v 1ms vpp3=gnd vpp3=gnd vcc iovcc vci gnd rs=0, db=16h0000 rs=0, db=16h0000 rs=0, db=16h0000 rs=0, db=16h0000 ra4h:calb=1 nv memory write sequence nv memory read sequence write time 100ms~200ms 9.00.3v 7.50.3v 1ms or more 2ms or more 100ms~ 200ms 1ms or more 2ms or more wait 1/fosc x 8 yes no power supply (vcc, vci, iovcc) on power supply (vcc, vci, iovcc) on power on reset power on reset vcc iovcc vci or vcc, iovcc, vci simultaneously vcc iovcc vci or vcc, iovcc, vci simultaneously nv memory data read r28h: instruction read r29h: instruction read r2ah: instruction read 1ms or more nv memory dummy read ra0: (invalid data) nv memory write end nv memory write start set nv memory write data nv memory write to other address? figure 85 nv memory write/read sequences
R61503U recommended resistance/connection example rev0.2 2006.06.26 testo1 Q25ohm vpp1 dummy8 vpp1 dummy7 vpp1 vpp1 vgldmy4 vpp1 g1 Q15ohm vpp2 g3 vpp2 g5 vpp2 vpp2 g7 vpp2 g9 vpp2 vpp2 Q25ohm vpp3 vpp3 vpp3 vpp3 vpp3 vpp3 vpp3 iognddum1 test1 test2 im0/id Q200ohm im0/id im1 Q200ohm im1 im2 Q200ohm im2 im3 Q200ohm im3 iovccdum1 reset* Q200ohm reset* vsync Q60ohm vsync hsync Q60ohm hsync dotclk Q60ohm dotclk enable Q60ohm enable db17 Q60ohm db17 db16 Q60ohm db16 db15 Q60ohm db15 g211 db14 Q60ohm db14 g213 db13 Q60ohm db13 g215 db12 Q60ohm db12 g217 db11 Q60ohm db11 g219 db10 Q60ohm db10 vgldmy3 db9 Q60ohm db9 dummy6 db8 Q60ohm db8 iognddum2 db7 Q60ohm db7 db6 Q60ohm db6 db5 Q60ohm db5 db4 Q60ohm db4 db3 Q60ohm db3 dummy5 db2 Q60ohm db2 s1 db1 Q60ohm db1 s2 db0 Q60ohm db0 s3 sdo Q60ohm sdo s4 sdi Q60ohm sdi s5 rd* Q60ohm rd* s6 wr*/scl Q60ohm wr*/scl s7 rs Q60ohm rs s8 cs* Q60ohm cs* exdum1 exdum2 exdum3 exdum4 flm Q60ohm flm iovccdum2 Q60ohm osc1 testo2 testo3 Q60ohm osc2 testo4 vref Q100ohm vrefc Q100ohm vddtest Q10ohm iovcc iovcc iovcc iovcc Q5ohm vcc vcc vcc vcc vcc vcc Q5ohm vddout vddout vddout vddout vdd vdd 1uf/6v/b vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd Q5ohm gnd gnd gnd gnd gnd gnd gnd gnd gnd Q5ohm rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd Q5ohm agnd agnd agnd agnd agnd agnd agnd agnd Q200ohm vgs Q5ohm ddvdh ddvdh 1uf/10v/b ddvdh ddvdh ddvdh ddvdh 1uf/6v/b Q10ohm c11m c11m c11m c11m Q10ohm c11p c11p c11p c11p Q5ohm vci1 vci1 1uf/6v/b vci1 vci1 vci1 vci1 vci1 vci1 Q5ohm vci vci vci vci vci vci vci Q200ohm vcilvl testo5 1uf/6v/b Q25ohm c13p c13p c13p c13p Q25ohm c13m c13m c13m c13m 0.47uf/10v/b Q25ohm c22m s524 c22m s525 Q25ohm c22p s526 c22p s527 0.47uf/10v/b Q25ohm c21m s528 c21m dummy4 Q25ohm c21p c21p testo6 testo7 Q10ohm vgh dummy3 0.47uf/25v/b vgh vgldmy2 vgh g220 vgh g218 vgh g216 vgh g214 testo8 g212 testo9 Q10ohm vgl vgl 1uf/25v/b vgl vgl vgl vgl vgl testo10 0.1uf/10v/b testo11 Q20ohm vreg1out testa5 vcomr Q200ohm vcomr Q20ohm vcl 1uf/6v/b vcl vcl vcl 1uf/6v/b Q10ohm vcoml vcoml vcoml vcoml Q10ohm vcom vcom vcom vcom g10 vcom g8 1uf/10v/b Q10ohm vcomh g6 vcomh g4 vcomh g2 vcomh vgldmy1 testo12 dummy2 dummy1 fpc glass substrate R61503U staggered arrangement top view (bump view) 228um 228um (1-a) (2-a) (1-b) (2-b) user lti
R61503U specification rev.1.1, march 29, 2007, page 169 of 186 absolute maximum ratings table 82 item symbol unit value notes power supply voltage (1) vcc, iovcc v -0.3 ~ + 4.6 1, 2 power supply voltage (2) vci - agnd v -0.3 ~ + 4.6 1, 3 power supply voltage (3) ddvdh - agnd v -0.3 ~ + 6.5 1, 4 power supply voltage (4) vgh - vgl v +11.0 ~ + 30.0 1, 4 power supply voltage (5) agnd - vgl v +3.0 ~ +13.0 1, 7 power supply voltage (6) ddvdh - vgl v +7.0 ~ +19.0 1, 5 power supply voltage (7) vci - vgl v +5.5 ~ +16.8 1, 7 input voltage vt v -0.3 ~ vcc + 0.3 1 operating temperature topr c -40 ~ + 85 1, 8 storage temperature tstg c -55 ~ + 110 1 notes: 1. if used beyond the absolute maximum ratings, the lsi may permanently be damaged. it is strongly recommended to use the lsi under the condition within the electrical characteristics in normal operation. if exposed to the condition not within the electrical characteristics, it may affect the reliability of the device. 2. make sure vcc (high) gnd (low) and iovcc (high) gnd (low). 3. make sure vci (high) agnd (low). 4. make sure ddvdh (high) agnd (low). 5. make sure ddvdh (high) vgl (low). 6. make sure vgh (high) agnd (low). 7. make sure agnd (high) vgl (low). 8. the dc/ac characteristics of die and wafer products are guaranteed at 85 oc.
R61503U specification rev.1.1, march 29, 2007, page 170 of 186 electrical characteristics dc characteristics table 83 (vcc = 2.5v ~ 3.6v, iovcc = 1.65v ~ 3.6v, ta = -40c ~ 85c) see note 1 item symbol unit test condition min. typ. max. notes input high-level voltage v ih v iov cc = 1.65v ~ 3.6 v 0.8 x iov cc ? iov cc 2, 3 input low-level voltage v il v iov cc = 1.65v ~ 3.6 v ? 0.3 ? 0.2 x iov cc 2, 3 output high voltage (db0-17 pins, flm) v oh v iov cc = 1.65v ~ 3.6 v i oh = -0.1ma 0.8 x iovcc ? ? 2 output low voltage (db0-17 pins, flm) v ol v iov cc = 1.65 ~ 3.6 v i ol = 0.1ma ? ? 0.2 x iovcc 2 i/o leak current i li a vin = 0 ~ iovcc ?1 ? 1 4 current consumption: (iovcc-gnd)+(vcc-gnd) normal operation mode i op1 a fosc = 289khz (220 line drive), fflm=70hz, iovcc=vcc=rvcc=3.0v, ta=25c, ram data: ?0000?h ? 120 190 5, 6 current consumption: (iovcc-gnd)+(vcc-gnd) 8-color mode, 24-line partial display i op2 a fosc = 289khz (24 line partial drive), fflm=40hz, iovcc=vcc=rvcc=3.0v, ta=25c, ram data: ?0000?h ? 110 ? 6 current consumption: (iovcc-gnd)+(vcc-gnd) ram access mode 1 normal operation mode (hwm= ?0?) i ram1 ma tcycw=250ns, iovcc=2.40v, vcc=3.0v, ta=25c, 80-8bit i/f, consecutive ram access during display ? 5 ? 6 current consumption: (iovcc-gnd)+(vcc-gnd) ram access mode 2 high-speed write function (hwm= ?1?) i ram2 ma tcycw=250ns, iovcc=2.40v, vcc=3.0v, ta=25c, 80-8bit i/f, consecutive ram access during display ? 1.2 ? 6 current consumption: (iovcc-gnd)+(vcc-gnd) standby mode i st a iovcc=vcc=vci=3.0v, ta=50 c ? 30 110 5 current consumption: (iovcc-gnd)+(vcc-gnd) deep standby mode i dst a iovcc=vcc=vci=3.0v, ta=50 c ? 0.1 1.0 5 lcd power supply current (vci-gnd) 260k color display i ci1 ma iovcc=vcc=3.0v, vci=3.0v fosc =289khz (220 lines), fflm=70hz, ta=25 c, ram data:?0000?h, ap=11, dc0=000, dc1=010, b/c =eor=1, nw=000000, bt=000, vc=100, vrh=1000, vcm=010110, vdv=1110, panel load: none ? 1.0 1.5 5, 6 lcd power supply current (vci-gnd) 8-color mode i ci2 ma iovcc=vcc=3.0v, vci=3.0v fosc =289khz (24-line partial), fflm=40hz, ta=25 c, ram data:?0000?h, ap=11, dc0=000, dc1=010, b/c =eor=1, nw=000000, bt=000, vc=100, vrh=1000, vcm=010110, vdv=1110, cl=1, pts=111, panel load: none ? 0.4 ? 5, 6 output voltage dispersion vo m v ? ? 5 ? 7 average output voltage variance v m v ? ? ? 35 8
R61503U specification rev.1.1, march 29, 2007, page 171 of 186 step-up circuit characteristics table 84 item unit test condition min typ max notes step-up output voltage ddvdh v iovcc=vcc=vci=3.0v fosc =226khz, ta=25 c, ap=11, bt=000, dc0=000, dc1=010, vc=100, c11=c13=c21=c22=1[ f] / b characteristics, ddvdh=vgh=vgl=vcl=1[ f] / b characteristics, panel load: none, i load1 = -1[ma] 4.0 4.2 ? 10 vgh v iovcc=vcc=vci=3.0v fosc =226khz, ta=25 c, ap=11, bt=000, dc0=000, dc1=010, vc=100, c11=c13=c21=c22=1[ f] / b characteristics, ddvdh=vgh=vgl=vcl=1[ f] / b characteristics, panel load: none, i load1 = -100[ a] 12.6 13.1 ? 10 vgl v iovcc=vcc=vci=3.0v fosc =226khz, ta=25 c, ap=11, bt=000, dc0=000, dc1=010, vc=100, c11=c13=c21=c22=1[ f] / b characteristics, ddvdh=vgh=vgl=vcl=1[ f] / b characteristics, panel load: none, i load1 = 100[ a] -10.5 -11.1 ? 10 vcl v iovcc=vcc=vci=3.0v fosc =226khz, ta=25 c, ap=11, bt=000, dc0=000, dc1=010, vc=100, c11=c13=c21=c22=1[ f] / b characteristics, ddvdh=vgh=vgl=vcl=1[ f] / b characteristics, panel load: none, i load1 = +200[ a] -1.98 -2.0 ? 10 input voltage vci v 2.5 ? 3.3 ? ac characteristics (vcc=2.5v ~ 3.6v, iovcc = 1.65v ~ 3.6v, ta = ? 40c ~ +85c*) * see note 1 table 85 clock characteristics item symbol unit test condition min typ max not es rc oscillation clock f osc khz rf = 260 k vcc=3.0v 192 226 271 9
R61503U specification rev.1.1, march 29, 2007, page 172 of 186 80-system bus interface timing characteristics (18/16-bit i/f) table 86 normal write operation (hwm= ?0?), iovcc = 1.65v ~ 3.6v, vcc = 2.5v ~ 3.6v item symbol unit timing diagram min typ max write t cycw ns figure 89 120 ? ? bus cycle time read t cycr ns figure 89 450 ? ? write low-level pulse width pw lw ns figure 89 40 ? ? read low-level pulse width pw lr ns figure 89 200 ? ? write high-level pulse width pw hw ns figure 89 50 ? ? read high-level pulse width pw hr ns figure 89 250 ? ? write/read rise/fall time t wrr, wrf ns figure 89 ? ? 25 write (rs~cs*, wr*) 0 setup time read (rs~cs*, rd*) t as ns figure 89 10 ? ? address hold time t ah ns figure 89 2 ? ? write data setup time t dsw ns figure 89 25 ? ? write data hold time t h ns figure 89 5 ? ? read data delay time t ddr ns figure 89 ? ? 100 read data hold time t dhr ns figure 89 5 ? ? table 87 high-speed write function (hwm= ?1?), iovcc = 1.65v ~ 3.6v, vcc = 2.5v ~ 3.6v item symbol unit timing diagram min typ max write t cycw ns figure 89 80 ? ? bus cycle time read t cycr ns figure 89 450 ? ? write low-level pulse width pw lw ns figure 89 40 ? ? read low-level pulse width pw lr ns figure 89 250 ? ? write high-level pulse width pw hw ns figure 89 40 ? ? read high-level pulse width pw hr ns figure 89 200 ? ? write/read rise/fall time t wrr, wrf ns figure 89 ? ? 25 write (rs~cs*, wr*) 0 setup time read (rs~cs*, rd*) t as ns figure 89 10 ? ? address hold time t ah ns figure 89 2 ? ? write data setup time t dsw ns figure 89 25 ? ? write data hold time t h ns figure 89 5 ? ? read data delay time t ddr ns figure 89 ? ? 100 read data hold time t dhr ns figure 89 5 ? ?
R61503U specification rev.1.1, march 29, 2007, page 173 of 186 80-system bus interface timing characteristics (9/8-bit i/f) table 88 normal/high-speed write function (hwm= ?0/1?), iovcc = 1.65v ~ 3.6v, vcc = 2.5v ~ 3.6v item symbol unit timing diagram min typ max write t cycw ns figure 89 70 ? ? bus cycle time read t cycr ns figure 89 400 ? ? write low-level pulse width pw lw ns figure 89 40 ? ? read low-level pulse width pw lr ns figure 89 200 ? ? write high-level pulse width pw hw ns figure 89 30 ? ? read high-level pulse width pw hr ns figure 89 200 ? ? write/read rise/fall time t wrr, wrf ns figure 89 ? ? 25 write (rs~cs*, wr*) 0 setup time read (rs~cs*, rd*) t as ns figure 89 10 ? ? address hold time t ah ns figure 89 2 ? ? write data setup time t dsw ns figure 89 25 ? ? write data hold time t h ns figure 89 5 ? ? read data delay time t ddr ns figure 89 ? ? 100 read data hold time t dhr ns figure 89 5 ? ? serial interface timing characteristics table 89 iovcc = 1.65v ~ 3.6v, vcc = 2.5v ~ 3.6v item symbol unit timing diagram min. typ. max. write (received) t scyc ns figure 90 100 - 20,000 serial clock cycle time read (transmitted) t scyc ns figure 90 350 - 20,000 write (received) t sch ns figure 90 40 - - serial clock high-level pulse width read (transmitted) t sch ns figure 90 150 - - write (received) t scl ns figure 90 40 - - serial clock low-level pulse width read (transmitted) t scl ns figure 90 150 - - serial clock rise/fall time t scr , t scf ns figure 90 - - 20 chip select setup time t csu ns figure 90 20 - - chip select hold time t ch ns figure 90 60 - - serial input data setup time t sisu ns figure 90 30 - - serial input data hold time t sih ns figure 90 30 - - serial output data delay time t sod ns figure 90 - - 130 serial output data hold time t soh ns figure 90 5 - -
R61503U specification rev.1.1, march 29, 2007, page 174 of 186 reset timing characteristics table 90 (iovcc = 1.65v ~ 3.6v, vcc = 2.5v ~ 3.6v) item symbol unit timing diagram min typ max reset low-level width t res ms figure 91 1 ? ? reset rise time t rres s figure 91 ? ? 10 rgb interface timing characteristics table 91 18/16-bit i/f, high-speed write function (hwm= ?1?), iovcc = 1.65v ~ 3.6v, vcc = 2.5v ~ 3.6v item symbol unit timing diagram min typ max vsync/hsync setup time tsyncs clocks figure 92 0 ? 1 enable setup time tens ns figure 92 10 ? ? enable hold time tenh ns figure 92 20 ? ? dotclk ?low? level pulse width pw dl ns figure 92 40 ? ? dotclk ?high? level pulse width pw dh ns figure 92 40 ? ? dotclk cycle time tcycd ns figure 92 100 ? ? data setup time tpds ns figure 92 10 ? ? data hold time tpdh ns figure 92 40 ? ? dotclk, vysnc, hsync rise/fall time trgbr, trgbf ns figure 92 ? ? 25 table 92 6-bit i/f, high-speed write function (hwm= ?1?), iovcc = 1.65v ~ 3.6v, vcc= 2.5v ~ 3.6v item symbol unit timing diagram min typ max vsync/hsync setup time tsyncs clocks figure 92 0 ? 1 enable setup time tens ns figure 92 10 ? ? enable hold time tenh ns figure 92 20 ? ? dotclk ?low? level pulse width pw dl ns figure 92 30 ? ? dotclk ?high? level pulse width pw dh ns figure 92 30 ? ? dotclk cycle time tcycd ns figure 92 80 ? ? data setup time tpds ns figure 92 10 ? ? data hold time tpdh ns figure 92 30 ? ? dotclk, vysnc, hsync rise/fall time trgbr, trgbf ns figure 92 ? ? 25
R61503U specification rev.1.1, march 29, 2007, page 175 of 186 lcd driver output characteristics table 93 item symbol unit test condition min typ max note driver output delay time t dd s vcc=3.0v, ddvdh=5.5v, vreg1out=5.0v, fosc =226khz, 220 line drive, ta=25 c rev=0, ap=010, vrp14-00=0, vrn14-00=0, pkp52-00=0, pkn52-00=0 prp12-00=0, prn12-00=0 load resistance r=10k ? , load capacitance c=20pf time to reach the target voltage level 35mv from the vcom polarity inversion timing transition from the same grayscale level at all source pins ? 38 ? 11
R61503U specification rev.1.1, march 29, 2007, page 176 of 186 notes to electrical characteristics 1. the dc/ac electrical characteristics of bare die and wafer products are guaranteed at 85 c. 2. the following figures illustrate the configurations of input, i/o, and output pins. iovcc pmos pmos nmos nmos iovcc pmos nmos vdd pmos nmos gnd iovcc pmos nmos output data iovcc pmos pmos nmos nmos output enable (input circuit) (output circuit: three states) input enable input enable (cs*) pins: wr*/scl, rd*, rs pins: db17-db0 pins: reset * , cs*, im3-1, im0/id, vsync, hsync, dotclk, enable, sdi, test1, test2 pins: osc1 iovcc pmos nmos pins: flm, sdo iognd iognd iognd iognd iognd figure 86 3. the test1, test2 pins must be grounded (gnd). the im3/2/1 and im0/id pins must be fixed at either iovcc or gnd. 4. this excludes the current in the output-drive mos. 5. this excludes the current in the input/output units. make sure that the input level is fixed because through current will increase in the input circuit when the cmos input level takes a middle range level. the current consumption is unaffected by whether the cs*pin is ?high? or ?low? while not accessing via interface pins.
R61503U specification rev.1.1, march 29, 2007, page 177 of 186 6. the relationship between voltages and the current consumption is as follows. figure 87 7. the output voltage deviation is the difference in the voltages from adjacent source pins for the same display data. this value is shown just for reference. 8. the average output voltage dispersion is the variance of average source-output voltage of different chips of the same product. the average source output voltage is measured for each chip with same display data.
R61503U specification rev.1.1, march 29, 2007, page 178 of 186 9. this applies to internal oscillators when using external oscillation resistor rf. oscillation frequency depends on the capacitances osc1 and osc2. make the wiring between osc1 and osc2 as short as possible. figure 88 10. the wiring resistance when the R61503U is mounted on the glass substrate is not taken into consideration. no load is applied on pins except those for measurement. see the reference data ?load current characteristics?.
R61503U specification rev.1.1, march 29, 2007, page 179 of 186 figure 89
R61503U specification rev.1.1, march 29, 2007, page 180 of 186 11. the liquid crystal driver output delay time depends on the load on the liquid crystal panel. adjust the frame frequency and the cycle per line by checking the quality of display on the actual panel in use. :? :?:? :?:? :?:? :?:? :?:? :?:? :? :? :?:? :?:? :?:? :?:? :?:? :?:? :? :? :? :? :? :?:? :?:? :?:? :? :? :?:? :?:? :?:? :?:? :?:? :?:? lcd driver output delay time tdd ( ? s) vcom output delay time ( ? s) load capacitance (pf) load capacitance (pf) (vcom "h" level is settling.) figure 90 test circuits :w test point test point test point load capacitance c: 20 pf load capacitance c: 20 pf 50 pf load resistance r: 40 load resistance r: 10k load circuit for testing lcd driver output characteristics [lcd output: s1-s528] load circuit for testing ac characteristics [data bus: db17-db0] load circuit for testing vcom output characteristics figure 91
R61503U specification rev.1.1, march 29, 2007, page 181 of 186 timing characteristics 80-system bus interface tddr tdhr vil vil twrr vih vil vih vil vil vih vil vih vih vil vih rs cs* wr* rd* tas tah pwhw,pwhr twrr tcycw, tcycr vih vil db17-0 vih tdsw th note 2) vih vil db17-0 vih note 2) write data read data pwlw, pwlr note 1) vih vil notes: 1. pwlw and pwlr are defined by the overlap period when cs* is low and when wr* or rd* is low. 2. fix unused db pins to either vcc or gnd level. figure 92
R61503U specification rev.1.1, march 29, 2007, page 182 of 186 clock synchronous serial interface output data vil vil vil vil vil tsc r vil vih tscyc vih sc l vih tcsu s di vih input data vih vil vih tch tsch tscl tscf vih input data tsisu tsish vol1 voh1 output data vol1 voh1 tsod tsoh start: s end: p sdo cs * vil figure 93 reset operation vil vih reset * tres vil trres figure 94
R61503U specification rev.1.1, march 29, 2007, page 183 of 186 rgb interface tpdh vil vih vil vih vil vil vsync hsync vih vih vil enable vih tens tenh vil vil vih vil dotclk vih pwdl pwdh vih vil db17-0 vih tpds write data tsyncs tcycd trgbf trgbr tr g bf tr g br vil vih vih vil figure 95 lcd driver output target grayscale voltage +/- 35mv target grayscale voltage +/- 35mv tdd v com s1-s528 figure 96
R61503U specification rev.1.1, march 29, 2007, page 184 of 186 keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is al ways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor gr ants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, yo u should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data , diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention t o additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability w hatsover for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this documen t, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. r enesas makes no representations, warr anties or guarantees regarding t he suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of hum an injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control , aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to u se renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officiers, direc tors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas s hall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the po ssibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment f or aging degradation or any other applicable measures. among others, sin ce the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products ma y not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from re nesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 2006. renesas technology corp., all rights reserved. printed in japan. colophon .1.0
R61503U specification rev.1.1, march 29, 2007, page 185 of 186 revision record rev. date contents of modification drawn by approved by 0.21 jun.28.2006 first issue 0.22 aug.25.2006 p.11 error correction (db17-10, 8-1 ? db17-13, 11-1) p.13 vci1 ? vci1 x 2, delete ?connect capacitors where they are required according to the step-up factor.? from c13+ ~ c22-. p.14 com ? von. p.15 agnd ? gnd. p.78 error correction (ib9: 0 ? divi[1], ib8: divi[1] ? divi[0], ib7: divi[0] ? 0) p.132 error correction. pp.140-141 add flm. p.164 error correction (7.0 0.3v ? 7.5 0.3v), add the write period setting. 0.23 sept.4.2006 p.161 change deep standby sequence. pp.162-163 add deep standby sequence. p.175 gnd ? iognd p.181 change lcd driver output. 0.24 dec.14, 2006 p.42 l7-0 ? 0 (ib15-8), 0 ? l7-0 (ib7-0) pp.46-47 change the formats, and add notes. p.174 18 ? 38 p.178 change the chart of driver output delay time, and add a load circuit for testing vcom output characteristics. 1.0 mar.19, 2007 pp.1, 2, 4, 7, 9, 12, 31, 40, 62, 71, 84, 86, 87, 165, 166, 167 eprom ? nv memory. p.7 change the description of liquid crystal drive. p.10 change the description of rs. p.11 change the connection of reset. p.14 change the description of vreg1out and vcom. p.17 400 m ? 280 m. p.48 add ptde setting in the table. p.62 change the range of vreg1out. pp.64-65 correct the order of ?power control 5? and ?power control 6?. pp.73-74 w/r ? w. p.86 power control 5 ? power control 6, and power control 6 ? power control 5. p.108 change the calculation formulas, and add clocks per line in the example. p.125 change the figure. p.128 reverse the waveform in the lower figure.
R61503U specification rev.1.1, march 29, 2007, page 186 of 186 rev. date contents of modification drawn by approved by p.129 reverse the waveform and change the numbers in the figure. p.130 17?h0dba ? 17?h0dbaf p.153 vinn ? vinn1. p.157 change the range of vreg1out. pp.162-164 add ?ra4h: ca lb = 1? and ?wait 1ms or more?. p.167 change the sequences. p.170 change the specs for iop1, iop2, ist, ici1, and ici2. p.171 change the specs for vgh. p.172 change the specs for tcycr and pwlr in the tables. pp.177-179 change the charts. 1.1 mar. 29, 2007 p.16 delete the description of chip and pad. p.130 delete the description of external display interface from the table. p.172 change write high-level pulse width (hwm = ?1?) (50 ? 40).

▲Up To Search▲

Price & Availability of R61503U

	To Download R61503U Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .